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參數(shù)資料
| 型號： | MPC8321VRAFDC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 75/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU PWRQUICC II 516-PBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 333MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 516-BBGA |
| 供應(yīng)商設(shè)備封裝： | 516-FPBGA（27x27） |
| 包裝： | 托盤 |
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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Freescale Semiconductor
77
System Design Information
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of package, without the inductance of vias.
Figure 44 shows the PLL power supply filter circuit.
Figure 44. PLL Power Supply Filter Circuit
24.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the MPC8323E can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8323E system, and the
MPC8323E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that
the system designer place at least one decoupling capacitor at each VDD, OVDD, and GVDD pins of the
MPC8323E. These decoupling capacitors should receive their power from separate VDD, OVDD, GVDD,
and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be
placed directly under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, and GVDD planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors—100–330 F (AVX TPS tantalum or Sanyo OSCON).
24.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVDD, or GVDD as required. Unused active high inputs
should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD, OVDD, and GND pins of the
MPC8323E.
24.5
Output Buffer DC Impedance
The MPC8323E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 45). The
VDD
AVDD (or L2AVDD)
2.2 F
GND
Low ESL Surface Mount Capacitors (<0.5 nH)
10
Ω
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