參數(shù)資料
型號(hào)： MPC8323ZQADDCA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA516
封裝： 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, PBGA-516
文件頁(yè)數(shù)： 74/82頁(yè)
文件大?。?/td> 1134K
代理商： MPC8323ZQADDCA
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
76
Freescale Semiconductor
System Design Information
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
TJ = TC + (RθJC × PD)
where:
TC = case temperature of the package (°C)
RθJC = junction-to-case thermal resistance (°C/W)
PD = power dissipation (W)
24 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8323E.
24.1
System Clocking
The MPC8323E includes three PLLs.
The system PLL (AVDD2) generates the system clock from the externally supplied CLKIN input.
The frequency ratio between the system and CLKIN is selected using the system PLL ratio
configuration bits as described in Section 22.4, “System PLL Configuration.”
The e300 core PLL (AVDD3) generates the core clock as a slave to the system clock. The frequency
ratio between the e300 core clock and the system clock is selected using the e300 PLL ratio
configuration bits as described in Section 22.5, “Core PLL Configuration.”
The QUICC Engine PLL (AVDD1) which uses the same reference as the system PLL. The QUICC
Engine block generates or uses external sources for all required serial interface clocks.
24.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins. The voltage
level at each AVDDn pin should always be equivalent to VDD, and preferably these voltages are derived
directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 44, one to each of the five AVDD pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
相關(guān)PDF資料
PDF描述
MPC8323ECZQADDCA 32-BIT, 266 MHz, RISC PROCESSOR, PBGA516
MPC8323CZQADDCA 32-BIT, 266 MHz, RISC PROCESSOR, PBGA516
MPC8323CZQAFDCA 32-BIT, 333 MHz, RISC PROCESSOR, PBGA516
MPC8323ECVRAFDCA 32-BIT, 333 MHz, RISC PROCESSOR, PBGA516
MPC8343ECZQAGDX 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MPC8323ZQAFDCA 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications
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