參數(shù)資料
型號: MPC8343CVRAGDX
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
封裝: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-620
文件頁數(shù): 49/92頁
文件大?。?/td> 987K
代理商: MPC8343CVRAGDX
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
53
SPI
16 SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8343E.
16.1
SPI DC Electrical Characteristics
Table 42 provides the DC electrical characteristics for the MPC8343E SPI.
16.2
SPI AC Timing Specifications
Table 43 and provide the SPI input and output AC timing specifications.
Table 42. SPI DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
2.0
OVDD+0.3
V
Input low voltage
VIL
-0.3
0.8
V
Input current
IIN
±5
A
Output high voltage
VOH
IOH = –8.0 mA
2.4
V
Output low voltage
VOL
IOL = 8.0 mA
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
Table 43. SPI AC Timing Specifications 1
Characteristic
Symbol 2
Min
Max
Unit
SPI outputs valid—Master mode (internal clock) delay
tNIKHOV
6ns
SPI outputs hold—Master mode (internal clock) delay
tNIKHOX
0.5
ns
SPI outputs valid—Slave mode (external clock) delay
tNEKHOV
8ns
SPI outputs hold—Slave mode (external clock) delay
tNEKHOX
2ns
SPI inputs—Master mode (internal clock input setup time
tNIIVKH
4ns
SPI inputs—Master mode (internal clock input hold time
tNIIXKH
0ns
SPI inputs—Slave mode (external clock) input setup time
tNEIVKH
4ns
SPI inputs—Slave mode (external clock) input hold time
tNEIXKH
2ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tNIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until
outputs (O) are invalid (X).
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