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參數(shù)資料
型號(hào): MPC8343EVRAGD
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 10/80頁(yè)
文件大小: 0K
描述: IC MPU PWRQUICC II PRO 620-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC83xx
處理器類(lèi)型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1.2V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤(pán)
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
18
Freescale Semiconductor
DDR and DDR2 SDRAM
Figure 5 illustrates the DDR input timing diagram showing the tDISKEW timing parameter.
Figure 5. DDR Input Timing Diagram
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20 shows the DDR and DDR2 output AC timing specifications.
266 MHz
–750
750
200 MHz
–750
750
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
will be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the equation: tDISKEW = ± (T/4 – abs (tCISKEW)); where T is the clock period and abs (tCISKEW) is the absolute
value of tCISKEW.
3. This specification applies only to the DDR interface.
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol 1
Min
Max
Unit
Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
tMCK
7.5
10
ns
2
ADDR/CMD/MODT output setup with respect to MCK
tDDKHAS
ns
3
400 MHz
1.95
333 MHz
2.40
266 MHz
3.15
200 MHz
4.20
Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications (continued)
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
MCK[n]
tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1
D0
tDISKEW
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