參數(shù)資料
型號: MPC8349CZUAGF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁數(shù): 62/88頁
文件大小: 1014K
代理商: MPC8349CZUAGF
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
65
Clocking
19 Clocking
Figure 39 shows the internal distribution of the clocks.
Figure 39. MPC8349E Clock Subsystem
The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device
is configured in PCI host or PCI agent mode. When the MPC8349E is configured as a PCI host device,
CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (
÷2) and the multiplexors for
PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether
CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select
whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the MPC8349E to function. When the
MPC8349E is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN
signal should be tied to GND.
Core PLL
System PLL
DDR
LBIU
LSYNC_IN
LSYNC_OUT
LCLK[0:2]
MCK[0:5]
core_clk
e300 Core
csb_clk to Rest
CLKIN
csb_clk
MPC8349E
6
DDR
Memory
Local Bus
PCI_CLK_OUT[0:7]
PCI_SYNC_OUT
PCI_CLK/
Clock
Unit
of the Device
ddr_clk
lbiu_clk
CFG_CLKIN_DIV
PCI Clock
PCI_SYNC_IN
Device
Memory
Device
/n
To Local Bus
Memory
Controller
To DDR
Memory
Controller
DLL
Clock
Div
/2
Divider
8
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