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參數(shù)資料
| 型號： | MPC8349CZUAJDB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 31/87頁 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC II PRO 672TBGA |
| 標準包裝： | 24 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 533MHz |
| 電壓： | 1.2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 672-LBGA |
| 供應商設備封裝： | 672-TBGA（35x35） |
| 包裝： | 托盤 |
| 配用： | MPC8349E-MITX-GP-ND - KIT REFERENCE PLATFORM MPC8349E MPC8349E-MITXE-ND - BOARD REFERENCE FOR MPC8349 MPC8349EA-MDS-PB-ND - KIT MODULAR DEV SYSTEM MPC8349E |
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
37
Local Bus
Figure 20 provides the AC test load for the local bus.
Figure 20. Local Bus C Test Load
Table 39. Local Bus General Timing Parameters—DLL Bypass9
Parameter
Symbol1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
15
—
ns
2
Input setup to local bus clock
tLBIVKH
7
—
ns
3, 4
Input hold from local bus clock
tLBIXKH
1.0
—
ns
3, 4
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
—
ns
5
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3—
ns
6
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
—
ns
7
Local bus clock to output valid
tLBKLOV
—3
ns
3
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ
—4
ns
8
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB)
for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one
(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output
(O) going invalid (X) or output hold time.
2. All timings are in reference to the falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or the rising edge
of LCLK0 (for all other inputs).
3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 × OVDD of the signal in question for 3.3 V
signaling levels.
4. Input timings are measured at the pin.
5. tLBOTOT1 should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the
load on the LAD output pins.
6. tLBOTOT2 should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than
the load on the LAD output pins.the
7. tLBOTOT3 should be used when RCWH[LALE] is not set and when the load on the LALE output pin equals to the load on the
LAD output pins.
8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
9. DLL bypass mode is not recommended for use at frequencies above 66 MHz.
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8349CZUAJFB | 功能描述:微處理器 - MPU 8349 TBGA W/O ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8349CZUALDB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MPC8349CZUALFB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MPC8349E | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC⑩ II Pro Integrated Host Processor Hardware Specifications |
| MPC8349E_07 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC⑩ II Pro Integrated Host Processor Hardware Specifications |
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