參數(shù)資料
型號(hào)： MPC8349ECZUAJFB
廠商： Freescale Semiconductor
文件頁數(shù)： 28/87頁
文件大小： 0K
描述： IC MPU POWERQUICC II PRO 672TBGA
標(biāo)準(zhǔn)包裝： 24
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 533MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 672-LBGA
供應(yīng)商設(shè)備封裝： 672-TBGA（35x35）
包裝： 托盤
配用： MPC8349E-MITX-GP-ND - KIT REFERENCE PLATFORM MPC8349E
MPC8349E-MITXE-ND - BOARD REFERENCE FOR MPC8349
MPC8349EA-MDS-PB-ND - KIT MODULAR DEV SYSTEM MPC8349E
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
34
Freescale Semiconductor
USB
9USB
This section provides the AC and DC electrical specifications for the USB interface of the MPC8349EA.
9.1
USB DC Electrical Characteristics
Table 35 provides the DC electrical characteristics for the USB interface.
9.2
USB AC Electrical Specifications
Table 36 describes the general timing parameters of the USB interface of the MPC8349EA.
Table 35. USB DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2OVDD +0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current
IIN
—±5
μA
High-level output voltage, IOH = –100 μAVOH
OVDD –0.2
—
V
Low-level output voltage, IOL = 100 μAVOL
—0.2
V
Table 36. USB General Timing Parameters (ULPI Mode Only)
Parameter
Symbol1
Min
Max
Unit
Notes
USB clock cycle time
tUSCK
15
—
ns
2–5
Input setup to USB clock—all inputs
tUSIVKH
4
—
ns
2–5
Input hold to USB clock—all inputs
tUSIXKH
1
—
ns
2–5
USB clock to output valid—all outputs
tUSKHOV
—
7
ns
2–5
Output hold from USB clock—all outputs
tUSKHOX
2
—
ns
2–5
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US) for
the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes
USB timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold
time.
2. All timings are in reference to USB clock.
3. All signals are measured from OVDD/2 of the rising edge of the USB clock to 0.4 × OVDD of the signal in question for 3.3 V
signaling levels.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to that of the leakage current specification.
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