參數(shù)資料
型號(hào): MPC8349EZUAJDB
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 63/87頁(yè)
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 672-TBGA
標(biāo)準(zhǔn)包裝: 24
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 533MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 672-LBGA
供應(yīng)商設(shè)備封裝: 672-TBGA(35x35)
包裝: 托盤
配用: MPC8349E-MITX-GP-ND - KIT REFERENCE PLATFORM MPC8349E
MPC8349E-MITXE-ND - BOARD REFERENCE FOR MPC8349
MPC8349EA-MDS-PB-ND - KIT MODULAR DEV SYSTEM MPC8349E
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
66
Freescale Semiconductor
Clocking
19 Clocking
Figure 41 shows the internal distribution of the clocks.
Figure 41. MPC8349EA Clock Subsystem
The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device
is configured in PCI host or PCI agent mode. When the MPC8349EA is configured as a PCI host device,
CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (
÷2) and the multiplexors for
PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether
CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select
whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the MPC8349EA to function. When the
device is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal
should be tied to GND.
Core PLL
System PLL
DDR
LBIU
LSYNC_IN
LSYNC_OUT
LCLK[0:2]
MCK[0:5]
core_clk
e300 Core
csb_clk to Rest
CLKIN
csb_clk
6
DDR
Memory
Local Bus
PCI_CLK_OUT[0:7]
PCI_SYNC_OUT
PCI_CLK/
Clock
Unit
of the Device
ddr_clk
lbiu_clk
CFG_CLKIN_DIV
PCI Clock
PCI_SYNC_IN
Device
Memory
Device
/n
To Local Bus
Memory
Controller
To DDR
Memory
Controller
DLL
Clock
Div
/2
Divider
8
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