參數(shù)資料
型號(hào): MPC8349VVAGF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-672
文件頁(yè)數(shù): 11/88頁(yè)
文件大?。?/td> 1014K
代理商: MPC8349VVAGF
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
19
DDR SDRAM
Figure 6 shows the DDR SDRAM output timing diagram for source synchronous mode.
Figure 6. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
Table 16 provides approximate delay information that can be expected for the address and command
signals of the DDR controller for various loadings, which can be useful for a system utilizing the DLL.
These numbers are the result of simulations for one topology. The delay numbers will strongly depend on
the topology used. These delay numbers show the total delay for the address and command to arrive at the
DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the
system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup
requirements at the DRAM.
Table 16. Expected Delays for Address/Command
Load
Delay
Unit
4 devices (12 pF)
3.0
ns
9 devices (27 pF)
3.6
ns
36 devices (108 pF) + 40 pF compensation capacitor
5.0
ns
36 devices (108 pF) + 80 pF compensation capacitor
5.2
ns
ADDR/CMD
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MCK[n]
tMCK
tDDKLDX
tDDKHDX
D1
D0
tDDKHAX,tDDKHCX
Write A0
NOOP
tDDKHAS,tDDKHCS
tDDKHMH
tDDKHME
tDDKHMP
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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