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| 型號： | MPC8349VVAJF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 533 MHz, MICROPROCESSOR, PBGA672 |
| 封裝： | 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-672 |
| 文件頁數(shù)： | 42/88頁 |
| 文件大?。?/td> | 1014K |
| 代理商： | MPC8349VVAJF |
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MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
47
PCI
Table 42 provides the PCI AC timing specifications at 33 MHz.
Figure 32 provides the AC test load for PCI.
Figure 32. PCI AC Test Load
PORESET to REQ64 hold time
tPCRHRX
050
ns
6
Notes:
1. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a
description of M66EN.
2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going
to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went
high (H) relative to the frame signal (F) going to the valid (V) state.
3. See the timing measurement conditions in the
PCI 2.2 Local Bus Specifications.
4. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.
5. Input timings are measured at the pin.
6. The setup and hold time is with respect to the rising edge of PORESET.
Table 42. PCI AC Timing Specifications at 33 MHz
Parameter
Symbol1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—11
ns
2
Output hold from clock
tPCKHOX
2—
ns
2
Clock to output high impedance
tPCKHOZ
—14
ns
2, 3
Input setup to clock
tPCIVKH
3.0
—
ns
2, 4
Input hold from clock
tPCIXKH
0—
ns
2, 4
REQ64 to PORESET setup time
tPCRVRH
5
—
clocks
5
PORESET to REQ64 hold time
tPCRHRX
050
ns
5
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going
to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went
high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the
PCI 2.2 Local Bus Specifications.
3. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. The setup and hold time is with respect to the rising edge of PORESET.
Table 41. PCI AC Timing Specifications at 66 MHz1 (continued)
Parameter
Symbol2
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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