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    參數(shù)資料
    型號(hào): MPC8358CZQAGDGA
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類(lèi): 微控制器/微處理器
    英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, PBGA668
    封裝: 29 X 29 MM, 1.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-668
    文件頁(yè)數(shù): 30/95頁(yè)
    文件大?。?/td> 1225K
    代理商: MPC8358CZQAGDGA
    MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
    36
    Freescale Semiconductor
    UCC Ethernet Controller: Three-Speed Ethernet, MII Management
    Figure 19 shows the RGMII and RTBI AC timing and multiplexing diagrams.
    Figure 19. RGMII and RTBI AC Timing and Multiplexing Diagrams
    GTX_CLK125 reference clock duty cycle
    tG125H/tG125
    47
    53
    %
    Notes:
    1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
    RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (Rx) clock. Note also that the
    notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
    the subscript is skew (SK) followed by the clock that is being skewed (RGT).
    2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
    will be added to the associated clock signal.
    3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
    4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
    as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned
    between.
    5. Duty cycle reference is LVDD/2.
    6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
    7. In rev. 2.1 silicon, due to errata, tSKRGTKHDX minimum is –0.65 ns for UCC2 option 1 and –0.9 for UCC2 option 2, and
    tSKRGTKHDV maximum is 0.75 ns for UCC1 and UCC2 option 1 and 0.85 for UCC2 option 2. UCC1 does meet tSKRGTKHDX
    minimum for rev. 2.1 silicon.
    Table 34. RGMII and RTBI AC Timing Specifications (continued)
    At recommended operating conditions with LVDD of 2.5 V ± 5%.
    Parameter/Condition
    Symbol1
    Min
    Typ
    Max
    Unit
    Notes
    GTX_CLK
    tRGT
    tRGTH
    tSKRGTKHDX
    TX_CTL
    TXD[8:5]
    TXD[7:4]
    TXD[9]
    TXERR
    TXD[4]
    TXEN
    TXD[3:0]
    (At Transmitter)
    TXD[8:5][3:0]
    TXD[7:4][3:0]
    TX_CLK
    (At PHY)
    RX_CTL
    RXD[8:5]
    RXD[7:4]
    RXD[9]
    RXERR
    RXD[4]
    RXDV
    RXD[3:0]
    RXD[8:5][3:0]
    RXD[7:4][3:0]
    RX_CLK
    (At PHY)
    tSKRGTKHDX
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