參數(shù)資料
型號(hào)： MPC8358ECZQAGDDA
廠(chǎng)商： Freescale Semiconductor
文件頁(yè)數(shù)： 2/4頁(yè)
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II PRO 668PBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC83xx
處理器類(lèi)型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1.2V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 668-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 668-PBGA-PGE（29x29）
包裝： 托盤(pán)
Connectivity
The MPC8360E processor is designed to
support a wide range of communications
interfaces, such as MII, RMII, GMII, TBI,
RTBI, NMSI, UTOPIA, POS and TDM.
The dual 32-bit DDR memory controllers
help to ensure high-speed memory
access and a local system bus operating
up to 133 MHz. Additional system
connectivity is supplied by dual UART,
dual inter-integrated circuit (I2C), dual serial
peripheral interface (SPI), PCI interfaces
and Universal Serial Bus (USB) interface
(USB 2.0 full/low speed compatible).
Integrated Security
The MPC8360E and MPC8358E
processors feature integrated security
with the powerfully integrated security
engine derived from Freescale’s security
coprocessor product line. Integrated
security supports DES, 3DES, MD-5, SHA-1,
AES and ARC-4 encryption algorithms, as
well as a public key accelerator and an
on-chip random number generator. The
integrated security engine is capable of
single-pass encryption and authentication,
as required by IPsec, the IEEE 802.11i
standard and other security protocols.
Typical Applications
DSL infrastructure
DSLAMs
MTUs
Wireless infrastructure
Base transceiver station (BTS)
Base station controller (BSC)
Radio network controller (RNC)
Node B
Small and medium enterprise (SME) routers
Intrusion detection/protection
system (IDS/IPS)
Secure VPN
Firewall
Add/drop multiplexers and digital
cross connects
Integrated voice routers and digital
IP-based private automatic branch
exchange (PABX)
Multi-service access nodes (MSAN)
Industrial and general-purpose
networking
QUICC Engine
Freescale’s QUICC Engine technology
includes two optimized RISC processors
supporting a wide range of protocols while
providing high data throughput of up to
1.2 Gbps. Flexibility is provided by the
eight unified communications controllers
(UCCs) providing support for Fast Ethernet,
Gigabit Ethernet, high-level data link control
(HDLC) and ATM/POS at up to OC-12
speeds. The MPC8360E and MPC8358E
support connectivity up to eight T1/E1s.
The MPC8360E supports eight TDMs
and the MPC8358E supports four TDMs,
with each TDM capable of supporting a
clear channel T3/E3. One multi-channel
communications controller (MCC) on the
MPC8360E supports up to 256 x 64 kbps
HDLC or transparent channels.
To simplify the transition from current
PowerQUICC designs, the advanced
QUICC Engine technology maintains a
high degree of software compatibility
with previous-generation PowerQUICC
processor-based designs. This helps ease
migration issues, reduce development costs
and speed time to market.
The QUICC Engine technology builds upon
the PowerQUICC shrink-wrapped software
protocol support and provides enhancements
in terms of interworking, parsing, switching
and forwarding. A full set of configurable
driver software and initialization support
will also be available.
Interworking
With the potential to offer three revenue
streams from a single IP packet network,
the triple play of voice, video and data is the
goal of every telecom operator. IP is the key
enabler, and in time, it will be universal. Until
then, equipment has to interoperate between
circuit- and packet-switched networks and
between many standards and protocols.
The interoperability between standard
protocols is referred to as interworking.
The QUICC Engine block supports
ATM-to-Ethernet interworking without
CPU intervention in support of the
industry-standard RFC2684 specification.
In addition, it can support MC/MLPPP to
Ethernet interworking.
It is able to perform powerful table lookup
functions including multiple fields from
Layers 2 to 4 without CPU intervention.
Key Advantages
High-performance, low-power and
cost-effective communications
processor solution
Convergence for packet-based networks
Compatibility with current PowerQUICC
offerings
Cost-effective solution at the chip
and system level
Advanced QUICC Engine technology
supporting a wide range of protocols
and associated interworking
DDR memory support—one 64-bit or
2 x 32-bit interfaces
Low risk when transitioning from legacy
to IP-based systems
Quick to market enabled by
software compatibility
Low bill of material (BOM) cost
Product Family Highlights
e300 core, built on Power Architecture
technology (enhanced version of the 603e
core with larger caches)
DDR memory controller, 1 x 32/64-bit or
2 x 32-bit, up to 333 MHz
QUICC Engine technology with eight
communications interfaces supporting
Fast Ethernet, Gigabit Ethernet, ATM,
POS, HDLC, asynchronous HDLC,
UART and transparent
32-bit PCI interface
32-bit local bus interface
Optional integrated security
Technical Specifications
e300 Power Architecture core operating
from 266 MHz to 667 MHz
32-bit, high-performance superscalar core
1,261 MIPS at 667 MHz; 503 MIPS
at 266 MHz
Double-precision floating point, integer,
load/store, system register and branch
processor units
32 KB data and 32 KB instruction cache
with line-locking support
QUICC Engine technology initially operating
up to 500 MHz
Two 32-bit RISC controllers
for flexible support of the
communications peripherals
Serial DMA channel for receive and
transmit on all serial channels
QUICC Engine peripheral request
interface for Integrated Security, PCI,
IEEE Std 1588
Eight UCCs supporting the following
protocols and interfaces:
10/100/1000 Mbps Ethernet
IEEE Std 1588 protocol supported
ATM SAR supporting AAL5, AAL2,
AAL1, AAL0, TM 4.0 CBR, VBR,
UBR traffic types, up to 64 KB
external connections
Inverse multiplexing for ATM (IMA)
POS up to 622 Mbps
Transparent
HDLC
Multi-link, multi-class PPP
HDLC bus
UART
BISYNC
One multi-channel communications
controller (MCC), supporting:
256 TDM channels
Transparent and HDLC mode
per channel
Support for Signaling System
Number 7 (SS7)
Almost any combination of subgroups
can be multiplexed to single or multiple
TDM interfaces
Two UTOPIA/POS interfaces supporting
up to 128 multi-PHY each
Two serial peripheral interfaces (SPIs)
Eight TDM interfaces, supporting:
Aggregate bandwidth of 64 kbps
and 256 channels
Maximum of 16 Mbps and 256
channels on a single TDM link
2,048 bytes of SI RAM (1,024 entries)
Eight programmable strobes
Bit or byte resolution
Independent transmit and receive
routing, frame synchronization
T1, CEPT, T1/E1, T3/E3, pulse-code
modulation highway, ISDN primary/basic
rate, Freescale interchip digital link (IDL)
and user-defined TDM serial interfaces
16 independent baud rate generators
Four independent 16-bit timers that can
be interconnected as two 32-bit timers
Two SPI ports that can be configured
as an Ethernet management port for
management data input/output (MDIO),
while the other can be configured for
cost-efffective serial peripherals; the
SPI also has a CPU mode that can
be configured by the CPU and not
through the QUICC Engine
USB interface
(USB 2.0 full/low speed compatible)
DDR memory controller
Programmable timing supporting
DDR-1/2 SDRAM
2 x 32-bit (MPC8360E only) or
1 x 32/64-bit data interface; up to
333 MHz data rate
Four banks of memory, each up to 1 GB
Full ECC support
PCI interface
One 32-bit PCI 2.3 bus controller
(3.3V I/O; up to 66 MHz)
Integrated security (MPC8360E and
MPC8358E only)
Public key execution
(RSA and Diffie-Hellman)
Data encryption standard execution
(DES and 3DES)
Advanced encryption standard
(AES) execution
ARC-4 execution
(RC4-compatible algorithm)
Message digest execution
(SHA, MD5, HMAC)
Random number generation (RNG)
Local bus controller
Multiplexed 32-bit address and
data operating up to 133 MHz
32-, 16- and 8-bit port
sizes controlled by on-chip
memory controller
Dual UART (DUART)
Dual I2C interfaces
(master or slave mode)
Four-channel DMA controller
General-purpose parallel I/O
IEEE 1149.1 JTAG test access port
Package option: 37.5 mm X 37.5 mm
740 TBGA (MPC8360E, MPC8358E);
29 mm x 29 mm 668 PBGA (MPC8358 only)
Process technology: 130 nm CMOS
Voltage: 1.2V core voltage with 3.3V,
2.5V and 1.8V I/O
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8358ECZQAGDGA 功能描述:微處理器 - MPU 8358 PBGA ENCRP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8358ECZUADDE 功能描述:微處理器 - MPU 8360 TBGA ENCRP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8358ECZUADDEA 功能描述:微處理器 - MPU 8360 TBGA C ENCRP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8358ECZUADDGA 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:MPC8360E/MPC8358E PowerQUICC II Pro Processor
MPC8358ECZUAGDEA 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:MPC8360E/MPC8358E PowerQUICC II Pro Processor
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