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參數(shù)資料
型號(hào): MPC8358VRAGDGA
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 44/95頁(yè)
文件大小: 0K
描述: MPU POWERQUICC II PRO 668-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC83xx
處理器類(lèi)型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1.2V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 668-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 668-PBGA-PGE(29x29)
包裝: 托盤(pán)
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
Freescale Semiconductor
49
I
2C
11 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8358E.
11.1
I2C DC Electrical Characteristics
Table 43 provides the DC electrical characteristics for the I2C interface of the device.
11.2
I2C AC Electrical Specifications
Table 44 provides the AC timing parameters for the I2C interface of the device.
Table 43. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 10%.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7
× OVDD
OVDD + 0.3
V
Input low voltage level
VIL
–0.3
0.3
× OVDD
V—
Low level output voltage
VOL
00.4
V
1
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF
tI2KLKV
20 + 0.1
× CB
250
ns
2
Pulse width of spikes which must be suppressed by the input
filter
tI2KHKL
050
ns
3
Capacitance for each I/O pin
CI
—10
pF
Input current (0 V
≤ VIN ≤ OVDD)IIN
—±10
μA4
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the
MPC8360E Integrated Communications Processor Family Reference Manual for information on the digital filter
used.
4. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
Table 44. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 43).
Parameter
Symbol1
Min
Max
Unit
SCL clock frequency
fI2C
0400
kHz
Low period of the SCL clock
tI2CL
1.3
μs
High period of the SCL clock
tI2CH
0.6
μs
Setup time for a repeated START condition
tI2SVKH
0.6
μs
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
tI2SXKL
0.6
μs
Data setup time
tI2DVKH
100
ns
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