參數(shù)資料
型號(hào): MPC8358ZQAGDGA
廠(chǎng)商: Freescale Semiconductor
文件頁(yè)數(shù): 22/95頁(yè)
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 668-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC83xx
處理器類(lèi)型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1.2V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 668-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 668-PBGA-PGE(29x29)
包裝: 托盤(pán)
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
Freescale Semiconductor
29
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 10 shows the GMII receive AC timing diagram.
Figure 10. GMII Receive AC Timing Diagram
8.2.2
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.2.1
MII Transmit AC Timing Specifications
Table 28 provides the MII transmit AC timing specifications.
Table 28. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
TX_CLK clock period 10 Mbps
tMTX
—400
ns
TX_CLK clock period 100 Mbps
tMTX
—40
ns
TX_CLK duty cycle
tMTXH/tMTX
35
65
%
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
tMTKHDX
tMTKHDV
1
5—
15
ns
TX_CLK data clock rise time, (20% to 80%)
tMTXR
1.0
4.0
ns
TX_CLK data clock fall time, (80% to 20%)
tMTXF
1.0
4.0
ns
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit
timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,
the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.
For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
RX_CLK
RXD[7:0]
tGRDXKH
tGRX
tGRXH
tGRXR
tGRXF
tGRDVKH
RX_DV
RX_ER
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