參數(shù)資料
型號(hào): MPC8360CVVAJDHA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA740
封裝: 37.50 X 37.50 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-740
文件頁(yè)數(shù): 49/102頁(yè)
文件大小: 606K
代理商: MPC8360CVVAJDHA
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
50
Freescale Semiconductor
PCI AC Electrical Specifications
This figure provides the AC test load for PCI.
Figure 36. PCI AC Test Load
Clock to output high impedance
tPCKHOZ
—14
ns
Input setup to clock
tPCIVKH
3.0
ns
Input hold from clock
tPCIXKH
0.3
ns
2, 4, 6
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing
(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference
(K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset
(R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. In rev. 2.0 silicon, due to errata, tPCIHOV maximum is 6.6 ns. Refer to Errata PCI21 in Chip Errata for the MPC8360E, Rev. 1.
6. In rev. 2.0 silicon, due to errata, tPCIXKH minimum is 1 ns. Refer to Errata PCI17 in Chip Errata for the MPC8360E, Rev. 1.
Table 48. PCI AC Timing Specifications at 33 MHz
Parameter
Symbol1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—11
ns
Output hold from clock
tPCKHOX
2—
ns
Clock to output high impedance
tPCKHOZ
—14
ns
Input setup to clock
tPCIVKH
7.0
ns
Input hold from clock
tPCIXKH
0.3
ns
2, 4, 5
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI
timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS,
reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time
hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. In rev. 2.0 silicon, due to errata, tPCIXKH minimum is 1 ns. Refer to Errata PCI17 in Chip Errata for the MPC8360E, Rev. 1.
Table 47. PCI AC Timing Specifications at 66 MHz (continued)
Parameter
Symbol1
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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