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參數(shù)資料
| 型號： | MPC8360CVVAJFGA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA740 |
| 封裝： | 37.50 X 37.50 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-740 |
| 文件頁數(shù)： | 55/102頁 |
| 文件大小： | 606K |
| 代理商： | MPC8360CVVAJFGA |
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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
56
Freescale Semiconductor
TDM/SI DC Electrical Characteristics
17
TDM/SI
This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial interface of the
MPC8360E/58E.
17.1
TDM/SI DC Electrical Characteristics
This table provides the DC electrical characteristics for the device TDM/SI.
17.2
TDM/SI AC Timing Specifications
This table provides the TDM/SI input and output AC timing specifications.
This figure provides the AC test load for the TDM/SI.
Figure 44. TDM/SI AC Test Load
Figure 45 represents the AC timing from Table 56. Note that although the specifications generally reference the rising edge of
the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Table 57. TDM/SI DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –2.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.5
V
Input high voltage
VIH
—2.0
OVDD + 0.3
V
Input low voltage
VIL
—–0.3
0.8
V
Input current
IIN
0 V
≤VIN ≤OVDD
—±10
μA
Table 58. TDM/SI AC Timing Specifications1
Characteristic
Symbol2
Min
Max3
Unit
TDM/SI outputs—External clock delay
tSEKHOV
210
ns
TDM/SI outputs—External clock high impedance
tSEKHOX
210
ns
TDM/SI inputs—External clock input setup time
tSEIVKH
5—
ns
TDM/SI inputs—External clock input hold time
tSEIXKH
2—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSEKHOX symbolizes the TDM/SI
outputs external timing (SE) for the time tTDM/SI memory clock reference (K) goes from the high state (H) until outputs (O)
are invalid (X).
3. Timings are measured from the positive or negative edge of the clock, according to SIxMR [CE] and SITXCEI[TXCEIx].
Refer MPC8360E Integrated Communications Processor Reference Manual for more details.
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8360CVVAJFHA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360CVVALDGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360CVVALDHA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360CVVALFGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360CVVALFHA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
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