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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
90
Freescale Semiconductor
Suggested PLL Configurations
The following steps describe how to use above table. See
Example 1.
2.
Choose the up or down sections in the table according to input clock rate 33 MHz or 66 MHz.
3.
Select a suitable CSB and core clock rates from
Table 76. Copy the SPMF and CORE PLL configuration bits.
4.
Select a suitable QUICC Engine block clock rate from
Table 76. Copy the CEPMF and CEPDF configuration bits.
5.
Insert the chosen SPMF, COREPLL, CEPMF and CEPDF to the RCWL fields, respectively.
c5
10000
0
33
—
533
—
∞∞
c6
10001
0
33
—
566
—
∞
66 MHz CLKIN/PCI_SYNC_IN Options
s1h
0011
0000110
66
200
400
—
∞∞
∞
s2h
0011
0000101
66
200
500
—
∞∞
s3h
0011
0000110
66
200
600
—
∞
s4h
0100
0000011
66
266
400
—
∞∞
∞
s5h
0100
0000100
66
266
533
—
∞∞
s6h
0100
0000101
66
266
667
—
∞
s7h
0101
0000010
66
333
—
∞∞
∞
s8h
0101
0000011
66
333
500
—
s9h
0101
0000100
66
333
667
—
∞
c1h
00101
0
66
—
333
∞∞
∞
c2h
00110
0
66
—
400
∞∞
∞
c3h
00111
0
66
—
466
—
∞∞
c4h
01000
0
66
—
533
—
∞∞
c5h
01001
0
66
—
600
—
∞
Note:
1. The Conf No. consist of prefix, an index and a postfix. The prefix “s” and “c” stands for “syset” and “ce” respectively. The
postfix “h” stands for “high input clock.’”The index is a serial number.
Table 76. Suggested PLL Configurations (continued)
Conf
No.1
SPMF
CORE
PLL
CEPMF
CEPDF
Input
Clock Freq
(MHz)
CSB Freq
(MHz)
Core Freq
(MHz)
QUICC
Engine
Freq (MHz)
400
(MHz)
533
(MHz)
667
(MHz)