參數(shù)資料
型號: MPC8378CVRALG
廠商: Freescale Semiconductor
文件頁數(shù): 51/128頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 689-PBGA
標(biāo)準(zhǔn)包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
29
8.3.1.2
SGMII Receive AC Timing Specifications
This table provides the SGMII receive AC timing specifications. Source synchronous clocking is not
supported; the clock is recovered from the data.
This figure shows the SGMII receiver input compliance mask eye diagram.
Figure 10. SGMII Receiver Input Compliance Mask
Table 29. SGMII Receive AC Timing Specifications
At recommended operating conditions with XVDD_SRDS = 1.0 V ± 5%.
Parameter
Symbol
Min
Typical
Max
Unit
Note
Deterministic jitter tolerance
JD
0.37
UIp-p
Combined deterministic and random jitter tolerance
JDR
0.55
UIp-p
Sinusoidal jitter tolerance
JSIN
0.1
UIp-p
Total jitter tolerance
JT
0.65
UIp-p
Bit error ratio
BER
10-12
——
Unit interval
UI
799.92
800
800.08
ps
AC-coupling capacitor
CTX
5
200
nF
Notes:
1. Measured at the receiver.
2. Each UI is 800 ps ± 100 ppm.
3. The external AC coupling capacitor is required. It’s recommended to be placed near the device transmitter outputs.
0.275
0.4
0.6
0.725
01
VRX_DIFFp-p-max/2
VRX_DIFFp-p-min/2
0
–VRX_DIFFp-p-min/2
–VRX_DIFFp-p-max/2
Time (UI)
Recei
v
er
Di
ff
e
rent
ia
l
Input
V
o
lt
age
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