MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
4
1.4
Integrated Programmable Interrupt Controller (IPIC)
The integrated programmable interrupt controller (IPIC) implements the necessary functions to provide a flexible solution for
general-purpose interrupt control. The IPIC programming model is compatible with the MPC8260 interrupt controller, and it
supports 8 external and 34 internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller.
1.5
Power Management Controller (PMC)
The power management controller includes the following features:
Provides power management when the device is used in both host and agent modes
Supports PCI Power Management 1.2 D0, D1, D2, and D3hot states
Support for PME generation in PCI agent mode, PME detection in PCI host mode
Supports Wake-on-LAN (Magic Packet), USB, GPIO, and PCI (PME input as host)
Supports MPC8349E backward-compatibility mode
1.6
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) allows the device to exchange data between other PowerQUICC family chips, Ethernet
PHYs for configuration, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface (receive, transmit, clock,
and slave select). The SPI block consists of transmitter and receiver sections, an independent baud-rate generator, and a control
unit.
1.7
DMA Controller, Dual I2C, DUART, Enhanced Local Bus Controller
(eLBC), and Timers
The device provides an integrated four-channel DMA controller with the following features:
Allows chaining (both extended and direct) through local memory-mapped chain descriptors (accessible by local
masters)
Supports misaligned transfers
There are two I2C controllers. These synchronous, multi-master buses can be connected to additional devices for expansion and
system development.
The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550 programming models. 16-byte
FIFOs are supported for both the transmitter and the receiver.
The main component of the enhanced local bus controller (eLBC) is its memory controller, which provides a seamless interface
to many types of memory devices and peripherals. The memory controller is responsible for controlling eight memory banks
shared by a NAND Flash control machine (FCM), a general-purpose chip-select machine (GPCM), and up to three
user-programmable machines (UPMs). As such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash
EPROM, NAND Flash, EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other
peripherals. The eLBC external address latch enable (LALE) signal allows multiplexing of addresses with data signals to reduce
the device pin count.
The enhanced local bus controller also includes a number of data checking and protection features, such as data parity
generation and checking, write protection, and a bus monitor to ensure that each bus cycle is terminated within a user-specified
period. The local bus can operate at up to 133 MHz.
The system timers include the following features: periodic interrupt timer, real time clock, software watchdog timer, and two
general-purpose timer blocks.