參數(shù)資料
型號： MPC8378EVRAGGA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù)： 74/125頁
文件大?。?/td> 894K
代理商： MPC8378EVRAGGA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
52
11.2.1
Full-Speed Output Path (Write)
This figure provides the data and command output timing diagram.
Figure 31. Full Speed Output Path
11.2.1.1
Full-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on
the PCB.
No clock delay:
tSFSKHOV + tDATA_DELAY + tISU < tSFSCKL
Eqn. 1
With clock delay:
tSFSKHOV + tDATA_DELAY + tISU < tSFSCKL + tCLK_DELAY
Eqn. 2
tDATA_DELAY + tSFSCKL < tSFSCK + tCLK_DELAY – tISU – tSFSKHOV
Eqn. 3
This means that data can be delayed versus clock up to 11 ns in ideal case of tSFSCKL =20ns:
tDATA_DELAY + 20 < 40 + tCLK_DELAY – 5 – 4
tDATA_DELAY < 11 + tCLK_DELAY
11.2.1.2
Full-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on
the PCB.
tCLK_DELAY < tSFSCKL + tSFSKHOX + tDATA_DELAY – tIH
Eqn. 4
tCLK_DELAY + tIH – tSFSKHOX < tSFSCKL+ tDATA_DELAY
Eqn. 5
This means that clock can be delayed versus data up to 15 ns (external delay line) in ideal case of tSFSCLKL =20ns:
Input at the
MPC8378E Pins
SD CLK at the
MPC8378E Pin
Output Valid Time: tSFSKHOV
Output Hold Time: tSFSKHOX
tIH (5 ns)
tCLK_DELAY
SD CLK at
Driving
Edge
Sampling
Edge
the Card Pin
tISU (5 ns)
tDATA_DELAY
tSFSCKL
tSFSCK (Clock Cycle)
Output from the
MPC8378E Pins
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