This figure provides the AC test load" />
參數(shù)資料
型號(hào): MPC8378EVRALG
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 81/127頁(yè)
文件大?。?/td> 0K
描述: MPU PWRQUICC II 667MHZ 689TEPBGA
產(chǎn)品培訓(xùn)模塊: MPC837x PowerQUICC II Pro Processors
視頻文件: Introduction to the MPC837x Family
標(biāo)準(zhǔn)包裝: 27
系列: MPC83xx
處理器類(lèi)型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤(pán)
配用: MPC8377E-RDBA-ND - BOARD REF DES MPC8377 REV 2.1
MPC8377E-MDS-PB-ND - BOARD MODULAR DEV SYSTEM
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
57
This figure provides the AC test load for the I2C.
Figure 37. I2C AC Test Load
This figure shows the AC timing diagram for the I2C bus.
Figure 38. I2C Bus AC Timing Diagram
Data hold time
CBUS compatible masters
I2C bus devices
tI2DXKL
0
0.9
Setup time for STOP condition
tI2PVKH
0.6
μs—
Bus free time between a STOP and START condition
tI2KHDX
1.3
μs—
Noise margin at the LOW level for each connected device (including
hysteresis)
VNL
0.1
× OVDD
—V
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH
0.2
× OVDD
—V
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH
symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I
2C timing (I2) for the time that the data with
respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time.
Also, tI2PVKH symbolizes I
2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid
state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. This chip provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
Table 47. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 46).
Parameter
Symbol1
Min
Max
Unit
Note
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
Sr
S
SDA
SCL
tI2CF
tI2SXKL
tI2CL
tI2CH
tI2DXKL
tI2DVKH
tI2SXKL
tI2SVKH
tI2KHKL
tI2PVKH
tI2CR
tI2CF
PS
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MPC8378EVRALGA 功能描述:微處理器 - MPU 8378 PBGA ST PbFr W/ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8378EVRANDA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications
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MPC8378EVRANGA 功能描述:微處理器 - MPU 8378 PBGA ST PbFr W/ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324