參數(shù)資料
型號: MPC8378EVRANG
廠商: Freescale Semiconductor
文件頁數(shù): 99/127頁
文件大?。?/td> 0K
描述: MPU PWRQUICC II 800MHZ 689TEPBGA
標準包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 800MHz
電壓: 1.05V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
配用: MPC8377E-RDBA-ND - BOARD REF DES MPC8377 REV 2.1
MPC8377E-MDS-PB-ND - BOARD MODULAR DEV SYSTEM
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
73
16.3.2
Gen2i/3G Receiver (Rx) Specifications
This table provides the Gen2i or 3 Gbits/s differential receiver input DC characteristics for the SATA
interface.
This table provides the differential receiver output AC characteristics for the SATA interface at Gen2i or
3.0 Gbits/s transmission.
Deterministic jitter, data-data
250 UI
USATA_TXDJ250UI
0.35
UIp-p
Note:
1. Measured at Tx output pins peak to peak phase variation, random data pattern.
Table 61. Gen2i/3G Receiver Input DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Differential input voltage
VSATA_RXDIFF
275
500
750
mVp-p
Differential RX input impedance
ZSATA_RXSEIM
85
100
115
Ω
Note:
1. Voltage relative to common of either signal comprising a differential pair.
Table 62. Gen 2i/3G Receiver AC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Channel Speed
tCH_SPEED
—3.0
Gbps
Unit Interval
TUI
333.2
333.33
335.11
ps
Total jitter
fC3dB =fBAUD/10
USATA_TXTJfB/10
0.46
UIp-p
Total jitter
fC3dB =fBAUD/500
USATA_TXTJfB/500
0.60
UIp-p
Total jitter
fC3dB =fBAUD/1667
USATA_TXTJfB/1667
0.65
UIp-p
Deterministic jitter
fC3dB =fBAUD/10
USATA_TXDJfB/10
0.35
UIp-p
Deterministic jitter
fC3dB =fBAUD/500
USATA_TXDJfB/500
0.42
UIp-p
Deterministic jitter
fC3dB =fBAUD/1667
USATA_TXDJfB/1667
0.35
UIp-p
Note:
1. Measured at Tx output pins peak to peak phase variation, random data pattern.
Table 60. Gen 1i/1.5G Receiver AC Specifications (continued)
Parameter
Symbol
Min
Typical
Max
Units
Note
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