參數(shù)資料
型號(hào): MPC8379CVRALG
廠商: Freescale Semiconductor
文件頁數(shù): 47/117頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 689-PBGA
標(biāo)準(zhǔn)包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
35
10.2
Local Bus AC Electrical Specifications
This table describes the general timing parameters of the local bus interface of the device when in PLL
enable mode.
Table 37. Local Bus DC Electrical Characteristics (LBVDD =2.5 V)
At recommended operating conditions with LBVDD = 2.5 V.
Parameter
Conditions
Symbol
Min
Max
Unit
Supply voltage 2.5 V
LBVDD
2.37
2.73
V
Output high voltage
IOH = –1.0 mA
LBVDD = Min
VOH
2.00
V
Output low voltage
IOL = 1.0 mA
LBVDD = Min
VOL
—0.40
V
Input high voltage
LBVDD = Min
VIH
1.7
LBVDD + 0.3
V
Input low voltage
LBVDD = Min
VIL
–0.3
0.70
V
Input high current
VIN
1 = LBV
DD
IIH
—20
μA
Input low current
VIN
1 = GND
IIL
–20
μA
Table 38. Local Bus DC Electrical Characteristics (LBVDD =1.8 V)
At recommended operating conditions with LBVDD = 1.8 V.
Parameter
Conditions
Symbol
Min
Max
Unit
Supply voltage 1.8 V
LBVDD
1.71
1.89
V
Output high voltage
IOH = –1.0 mA
LBVDD = Min
VOH
LBVDD – 0.45
V
Output low voltage
IOL = 1.0 mA
LBVDD = Min
VOL
—0.45
V
Input high voltage
LBVDD = Min
VIH
0.65
× LBVDD
LBVDD + 0.3
V
Input low voltage
LBVDD = Min
VIL
–0.3
0.35
× LBVDD
V
Input high current
VIN
1 = LBV
DD
IIH
—10
μA
Input low current
VIN
1 = GND
IIL
–10
μA
Table 39. Local Bus General Timing Parameters—PLL Enable Mode
Parameter
Symbol1
Min
Max
Unit
Note
Local bus cycle time
tLBK
7.5
15
ns
Input setup to local bus clock (except LUPWAIT/LGTA)tLBIVKH
1.5
ns
Input hold from local bus clock
tLBIXKH
ns
LUPWAIT/LGTA input setup to local bus clock
tLBIVKH1
1.5
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3—
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
ns
Local bus clock to LALE rise
tLBKHLR
—4.5
ns
Local bus clock to output valid (except LALE)
tLBKHOV
—4.5
ns
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