13 I2
參數(shù)資料
型號： MPC8379EVRAJF
廠商： Freescale Semiconductor
文件頁數(shù)： 80/127頁
文件大小： 0K
描述： MPU PWRQUICC II 533MHZ 689TEPBGA
標(biāo)準(zhǔn)包裝： 27
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 533MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 689-TEPBGA II（31x31）
包裝： 托盤
配用： MPC8377E-RDBA-ND - BOARD REF DES MPC8377 REV 2.1
MPC8377E-MDS-PB-ND - BOARD MODULAR DEV SYSTEM
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
56
Freescale Semiconductor
13 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the chip.
13.1
I2C DC Electrical Characteristics
This table provides the DC electrical characteristics for the I2C interface of the chip.
13.2
I2C AC Electrical Specifications
This table provides the AC timing parameters for the I2C interface of the device.
Table 46. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 165 mV.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage level
VIH
0.7
× OVDD
OVDD + 0.3
V
—
Input low voltage level
VIL
–0.3
0.3
× OVDD
V—
Low level output voltage
VOL
00.2
× OVDD
Output fall time from VIH(min) to VIL(max) with a bus capacitance
from 10 to 400 pF
tI2KLKV
20 + 0.1
× CB
250
ns
Pulse width of spikes which must be suppressed by the input filter
tI2KHKL
050
ns
Capacitance for each I/O pin
CI
—10
pF
—
Input current
(0 V
≤ VIN ≤ OVDD)
IIN
—± 30
μA4
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the
MPC8379E PowerQUICC II Pro Integrated Host Processor Reference Manual for information on the digital filter
used.
4. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
Table 47. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 46).
Parameter
Symbol1
Min
Max
Unit
Note
SCL clock frequency
fI2C
0
400
kHz
—
Low period of the SCL clock
tI2CL
1.3
—
μs—
High period of the SCL clock
tI2CH
0.6
—
μs—
Setup time for a repeated START condition
tI2SVKH
0.6
—
μs—
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
tI2SXKL
0.6
—
μs—
Data setup time
tI2DVKH
100
—
ns
—
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