參數(shù)資料
型號: MPC8379EVRALG
廠商: Freescale Semiconductor
文件頁數(shù): 86/127頁
文件大?。?/td> 0K
描述: MPU PWRQUICC II 667MHZ 689TEPBGA
產(chǎn)品培訓模塊: MPC837x PowerQUICC II Pro Processors
視頻文件: Introduction to the MPC837x Family
標準包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
配用: MPC8377E-RDBA-ND - BOARD REF DES MPC8377 REV 2.1
MPC8377E-MDS-PB-ND - BOARD MODULAR DEV SYSTEM
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
61
15.2
AC Requirements for PCI Express SerDes Clocks
This table lists the PCI Express SerDes clock AC requirements.
15.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
15.4
Physical Layer Specifications
Following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the transport and data link layer, use the PCI Express Base
Specification, Rev. 1.0a.
NOTE
The voltage levels of the transmitter and the receiver depend on the SerDes
control registers which should be programmed at the recommended values
for PCI Express protocol (that is, L1_nVDD = 1.0 V).
Table 51. SD_REF_CLK and SD_REF_CLK AC Requirements
Parameter
Symbol
Min
Typical
Max
Unit
Note
REFCLK cycle time
tREF
—10
ns
REFCLK cycle-to-cycle jitter. Difference in the period of any
two adjacent REFCLK cycles.
tREFCJ
100
ps
REFCLK phase jitter peak-to-peak. Deviation in edge
location with respect to mean edge location.
tREFPJ
–50
+50
ps
SD_REF_CLK/_B cycle to cycle clock jitter (period jitter)
tCKCJ
100
ps
SD_REF_CLK/_B phase jitter peak-to-peak. Deviation in
edge location with respect to mean edge location.
tCKPJ
–50
+50
ps
Notes:
1. All options provide serial interface bit rate of 1.5 and 3.0 Gbps.
2. In a frequency band from 150 kHz to 15 MHz, at BER of 10-12.
3. Total peak-to-peak Deterministic Jitter “JD” should be less than or equal to 50 ps.
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