參數(shù)資料
型號: MPC8379EVRALGA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù): 70/114頁
文件大?。?/td> 1337K
代理商: MPC8379EVRALGA
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
59
Serial ATA (SATA)
15.1
Requirements for SATA REF_CLK
The reference clock is a single ended input clock required for the SATA interface operation. The AC
requirements for the SATA reference clock are listed in the Table 50.
Figure 42 shows the SATA reference clock timing waveform.
Figure 42. SATA Reference Clock Timing Waveform
15.2
Transmitter (Tx) Output Characteristics
This section discusses the Gen1i/1.5G and Gen2i/3G transmitter output characteristics for the SATA
interface.
Table 50. SATA Reference Clock Input Requirements
Parameter
Condition
Symbol
Min
Typical
Max
Unit
Notes
SD_REF_CLK/ SD_REF_CLK
frequency range
—tCLK_REF
100/125/150
MHz
1
SD_REF_CLK/ SD_REF_CLK
clock frequency tolerance
—tCLK_TOL
–350
0
+350
ppm
SD_REF_CLK/ SD_REF_CLK
reference clock duty cycle
Measured at 1.6V
tCLK_DUTY
40
50
60
%
SD_REF_CLK/ SD_REF_CLK
cycle to cycle Clock jitter (period
jitter)
Cycle-to-cycle at
ref clock input
tCLK_CJ
100
ps
SD_REF_CLK/ SD_REF_CLK total
reference clock jitter, phase jitter
(peak-peak)
Peak-to-peak jitter
at ref clock input
tCLK_PJ
–50
+50
ps
2, 3
Note:
1 Only 100/125/150 MHz have been tested, othe in between values will not work correctly with the rest of the system.
2 In a frequency band from 150 kHz to 15 MHz at BER of 10-12.
3 Total peak to peak Deterministic Jitter "D
J" should be less than or equal to 50 ps.
TH
TL
Ref_CLK
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