參數(shù)資料
型號： MPC8379VRALGA
廠商： Freescale Semiconductor
文件頁數(shù)： 45/117頁
文件大?。?/td> 0K
描述： MPU POWERQUICC II 667MHZ 689PBGA
標(biāo)準(zhǔn)包裝： 27
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 667MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 689-TEPBGA II（31x31）
包裝： 托盤
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
33
9.1
USB DC Electrical Characteristics
This table provides the DC electrical characteristics for the ULPI interface at recommended
OVDD = 3.3 V ± 165 mV.
9.2
USB AC Electrical Specifications
This table describes the general timing parameters of the USB interface of the device.
Table 34. USB DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Note
High-level input voltage
VIH
2OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current
IIN
—±30
μA2
High-level output voltage, IOH = –100 μAVOH
OVDD – 0.2
—
V
—
Low-level output voltage, IOL = 100 μAVOL
—0.2
V
—
Notes:
1. The minimum VIL and maximum VIH values are based on the respective minimum and maximum OVIN values found in
2. The symbol OVIN represents the input voltage of the supply and is referenced in Table 3.
Table 35. USB General Timing Parameters (ULPI Mode Only)
Parameter
Symbol 1
Min
Max
Unit
Note
USB clock cycle time
tUSCK
15
—
ns
Input setup to USB clock—all inputs
tUSIVKH
4
—
ns
Input hold to USB clock—all inputs
tUSIXKH
1
—
ns
USB clock to output valid—all outputs
tUSKHOV
—
7
ns
Output hold from USB clock—all outputs
tUSKHOX
2
—
ns
Notes:
1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US)
for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes
USB timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going invalid (X) or output hold
time.
2. All timings are in reference to the USB clock, USBDR_CLK.
3. All signals are measured from OVDD/2 of the rising edge of the USB clock to 0.4 × OVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered
through the component pin is less than or equal to that of the leakage current specification.
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