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參數(shù)資料
| 型號： | MPC850DEZT66A |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 70K |
| 代理商： | MPC850DEZT66A |
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MPC850/MPC850SE Technical Summary
MOTOROLA
— Fourteen internal interrupt sources
— Programmable priority between SCCs
— Programmable highest-priority request
Single socket PCMCIA-ATA interface
— Master (socket) interface, release 2.1 compliant
— Single PCMCIA socket
— Supports eight memory or I/O windows
Communications processor module (CPM)
— 32-bit, Harvard architecture, scalar RISC controller
— Communication specific commands (e.g., graceful stop transmit, close receive buffer
descriptor, RxBD)
— Up to 384 buffer descriptors
— Supports continuous mode transmission and reception on all serial channels
— Up to 8Kbytes of dual-port RAM
— Fourteen serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
On-chip 16- x 16-bit multiply-accumulate controller (MAC)
— One operation per clock. Two-clock latency, one-clock blockage.
— MAC operates concurrently with other instructions
— FIR loop: four clocks per four multiplies
Four baud rate generators
— Independent and can be connected to any serial communication controller (SCC) or serial
management controller (SMC)
— Allow changes during operation
— Autobaud support option
Two SCCs (serial communication controllers)
— QMC microcode for protocol processing of 64 time-division multiplexed channels
— Asynchronous Transfer Mode (ATM)
— Ethernet/IEEE 802.3, supporting full 10-Mbps operation
— HDLC/SDLC (all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
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