參數(shù)資料
型號(hào): MPC850DSLVR50BU
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 6/72頁(yè)
文件大小: 0K
描述: IC MPU PWRQUICC 50MHZ 256-PBGA
標(biāo)準(zhǔn)包裝: 60
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 50MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(23x23)
包裝: 托盤
MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
14
Freescale Semiconductor
Bus Signal Timing
B28c
CLKOUT falling edge to
WE[0–3] negated GPCM write
access TRLX = 0,1 CSNT = 1
write access TRLX = 0, CSNT =
1, EBDF = 1
7.00
14.00
11.00
18.00
9.00
16.00
0.375
50.00
ns
B28d
CLKOUT falling edge to CS
negated GPCM write access
TRLX = 0,1 CSNT = 1, ACS =
10 or ACS = 11, EBDF = 1
14.00
18.00
16.00
0.375
50.00
ns
B29
WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access, CSNT = 0
3.00
6.00
4.00
0.250
50.00
ns
B29a
WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 0 CSNT = 1,
EBDF = 0
8.00
13.00
11.00
0.500
50.00
ns
B29b
CS negated to D[0–31],
DP[0–3], high-Z GPCM write
access, ACS = 00, TRLX = 0 &
CSNT = 0
3.00
6.00
4.00
0.250
50.00
ns
B29c
CS negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 0, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
0
8.00
13.00
11.00
0.500
50.00
ns
B29d
WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
EBDF = 0
28.00
43.00
36.00
1.500
50.00
ns
B29e
CS negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
0
28.00
43.00
36.00
1.500
50.00
ns
B29f
WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
EBDF = 1
5.00
9.00
7.00
0.375
50.00
ns
B29g
CS negated to D[0–31],
DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
1
5.00
9.00
7.00
0.375
50.00
ns
Table 6. Bus Operation Timing 1 (continued)
Num
Characteristic
50 MHz
66 MHz
80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min
Max
Min
Max
Min
Max
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