參數(shù)資料
型號: MPC850ZT33
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA256
封裝: PLASTIC, BGA-256
文件頁數(shù): 6/12頁
文件大小: 70K
代理商: MPC850ZT33
MOTOROLA
MPC850/MPC850SE Technical Summary
3
least-recently used (LRU) replacement algorithm, lockable on-line granularity
— Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and
fully-associative instruction and data TLBs
— Memory management units support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes,
512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 8 protection groups
Advanced on-chip emulation debug mode
Data bus dynamic bus sizing for 8-, 16-, and 32-bit buses
— Supports traditional 68000 big-endian, traditional x86 little-endian and PowerPC little-endian
memory systems
— Twenty-six external address lines
Completely static design (0-MHz to 66-MHz operation)
System integration unit (SIU)
— Hardware bus monitor
— Spurious interrupt monitor
— Software watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— PowerPC decrementer
— PowerPC time base and real-time clock
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Memory controller (eight banks)
— Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM
(SDRAM), static random-access memory (SRAM), electrically programmable read-only
memory (EPROM), Flash EPROM, etc.
— Memory controller programmable to support most size and speed memory interfaces
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes, 32 Kbyte to 256 Mbyte
— Selectable write protection
— On-chip bus arbitration supports external bus master
— Special features for burst mode support
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
Interrupts
— Seven external interrupt request (IRQ) lines
— Eight port pins with interrupt capability
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