參數(shù)資料
型號(hào): MPC852TVR100
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Hardware Specifications
中文描述: 硬件規(guī)格
文件頁(yè)數(shù): 56/80頁(yè)
文件大小: 3080K
代理商: MPC852TVR100
MPC852T Hardware Specifications, Rev. 3.1
56
Freescale Semiconductor
FEC Electrical Characteristics
Figure 57. SPI Slave (CP = 1) Timing Diagram
15 FEC Electrical Characteristics
This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing
specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII
signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
15.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV,
MII_RX_ER, MII_RX_CLK)
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25MHz +1%. There is no minimum
frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency - 1%.
Table 25
provides information on the MII receive signal timing.
Table 25. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup
5
ns
M2
MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold
5
ns
M3
MII_RX_CLK pulse width high
35%
65%
MII_RX_CLK period
M4
MII_RX_CLK pulse width low
35%
65%
MII_RX_CLK period
SPIMOSI
(Input)
SPICLK
(CI=0)
(Input)
SPICLK
(CI=1)
(Input)
SPIMISO
(Output)
180
Data
181
182
msb
lsb
181
177
182
175
179
SPISEL
(Input)
174
Data
msb
lsb
Undef
178
176
182
msb
msb
172
173
173
171
170
181
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MPC852TVR100A 功能描述:微處理器 - MPU Ethernet 100 MHz RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC852TVR100A 制造商:Freescale Semiconductor 功能描述:IC COMMUNICATIONS CONTROLLER CMOS BGA
MPC852TVR50 制造商:Freescale Semiconductor 功能描述:
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