參數(shù)資料
型號: MPC8535AVTAQGA
廠商: Freescale Semiconductor
文件頁數(shù): 111/126頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 783FCPBGA
標準包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應商設備封裝: 783-FCPBGA(29x29)
包裝: 托盤
Electrical Characteristics
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
85
2.17.2
I2C AC Electrical Specifications
This table provides the AC timing parameters for the I
2C interfaces.
Pulse width of spikes which must be suppressed by the input
filter
tI2KHKL
050
ns
2
Input current each I/O pin (input voltage is between 0.1
×
OVDD and 0.9 × OVDD(max)
II
–10
10
μA3
Capacitance for each I/O pin
CI
—10
pF
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. See the
MPC8536E PowerQUICC III Integrated Processor Reference Manual for information on the digital filter used.
3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
Table 64. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 63).
Parameter
Symbol 1
Min
Max
Unit
Notes
SCL clock frequency
fI2C
0
400
kHz
Low period of the SCL clock
tI2CL
1.3
μs—
High period of the SCL clock
tI2CH
0.6
μs—
Setup time for a repeated START condition
tI2SVKH
0.6
μs—
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
tI2SXKL
0.6
μs—
Data setup time
tI2DVKH
100
ns
Data hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL
0
μs2
Data output delay time
tI2OVKL
—0.9
μs3
Set-up time for STOP condition
tI2PVKH
0.6
μs—
Rise time of both SDA and SCL signals
tI2CR
300
ns
4
Fall time of both SDA and SCL signals
tI2CF
300
ns
4
Table 63. I2C DC Electrical Characteristics (continued)
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
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