參數(shù)資料
型號: MPC8535BVTATHA
廠商: Freescale Semiconductor
文件頁數(shù): 62/126頁
文件大小: 0K
描述: MCU PWRQUICC II 1250MHZ 783-PBGA
標準包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.25GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
其它名稱: MPC8535BVTATH
MPC8535BVTATH-ND
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
40
2.9.1
Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1000 Mbps) — FIFO/GMII/MII/TBI/RGMII/RTBI/RMII Electrical
Characteristics
The electrical characteristics specified here apply to all FIFO mode, gigabit media independent interface (GMII), media
independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), reduced ten-bit
interface (RTBI), and reduced media independent interface (RMII) signals except management data input/output (MDIO) and
management data clock (MDC), and serial gigabit media independent interface (SGMII). The RGMII, RTBI and FIFO mode
interfaces are defined for 2.5 V, while the GMII, MII, RMII, and TBI interfaces can operate at 3.3V.
The GMII, MII, or TBI interface timing is compliant with IEEE 802.3. The RGMII and RTBI interfaces follow the Reduced
Gigabit Media-Independent Interface (RGMII) Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII
Consortium RMII Specification Version 1.2 (3/20/1998).
The electrical characteristics for MDIO and MDC are specified in Section 2.10, “Ethernet Management Interface Electrical
The electrical characteristics for SGMII is specified in Section 2.9.3, “SGMII Interface Electrical Characteristics.” The SGMII
interface conforms (with exceptions) to the Serial-GMII Specification Version 1.8.
2.9.1.1
GMII, MII, TBI, RGMII, RMII and RTBI DC Electrical Characteristics
All GMII, MII, TBI, RGMII, RMII and RTBI drivers and receivers comply with the DC parametric attributes specified in the
following tables. The RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC
EIA/JESD8-5.
Table 24. GMII, MII, RMII, and TBI DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage 3.3 V
LVDD
TVDD
3.13
3.47
V
1, 2
1 LV
DD supports eTSECs 1.
2 TV
DD supports eTSECs 3.
Output high voltage
(LVDD/TVDD = Min, IOH = –4.0 mA)
VOH
2.40
LVDD/TVDD + 0.3
V
Output low voltage
(LVDD/TVDD = Min, IOL = 4.0 mA)
VOL
GND
0.50
V
Input high voltage
VIH
1.90
LVDD/TVDD + 0.3
V
Input low voltage
VIL
–0.3
0.90
V
Input high current
(VIN = LVDD, VIN = TVDD)
IIH
—40
μA
1, 2,3
3 The symbol V
IN, in this case, represents the LVIN and TVIN symbols referenced in Table 1 and Table 2.
Input low current
(VIN = GND)
IIL
–600
μA
3
Notes:
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