參數(shù)資料
型號(hào): MPC8535CVTANGA
廠商: Freescale Semiconductor
文件頁數(shù): 75/126頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 783FCPBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 800MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
52
This figure shows the RMII transmit AC timing diagram.
Figure 26. RMII Transmit AC Timing Diagram
2.9.2.7.2
RMII Receive AC Timing Specifications
Rise time TSECn_TX_CLK (20%–80%)
tRMTR
1.0
2.0
ns
Fall time TSECn_TX_CLK (80%–20%)
tRMTF
1.0
2.0
ns
TSECn_TX_CLK to RMII data TXD[1:0], TX_EN delay
tRMTDX
2.0
10.0
ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX
symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid
(X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock
of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Table 37. RMII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
TSECn_RX_CLK clock period
tRMR
15.0
20.0
25.0
ns
TSECn_RX_CLK duty cycle
tRMRH
35
50
65
%
TSECn_RX_CLK peak-to-peak jitter
tRMRJ
250
ps
Rise time TSECn_RX_CLK (20%–80%)
tRMRR
1.0
2.0
ns
Table 36. RMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
TSECn_TX_CLK
TXD[1:0]
tRMTDX
tRMT
tRMTH
tRMTR
tRMTF
TX_EN
TX_ER
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