參數(shù)資料
型號: MPC8536AVTAKGA
廠商: Freescale Semiconductor
文件頁數(shù): 85/126頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 783FCPBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 600MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
Electrical Characteristics
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
61
The IEEE 1588 AC timing specifications are in the following table.
2.10
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals EC_MDIO (management data
input/output) and EC_MDC (management data clock). The electrical characteristics for GMII, SGMII, RGMII, RMII, TBI and
Table 43. eTSEC IEEE 1588 AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Note
TSEC_1588_CLK clock period
tT1588CLK
3.8
TTX_CLK*7
ns
1
TSEC_1588_CLK duty cycle
tT1588CLKH
/tT1588CLK
40
50
60
%
TSEC_1588_CLK peak-to-peak jitter
tT1588CLKINJ
——
250
ps
Rise time eTSEC_1588_CLK (20%–80%)
tT1588CLKINR
1.0
2.0
ns
Fall time eTSEC_1588_CLK (80%–20%)
tT1588CLKINF
1.0
2.0
ns
TSEC_1588_CLK_OUT clock period
tT1588CLKOUT
2*tT1588CLK
——ns
TSEC_1588_CLK_OUT duty cycle
tT1588CLKOTH
/tT1588CLKOUT
30
50
70
%
TSEC_1588_PULSE_OUT
tT1588OV
0.5
3.0
ns
TSEC_1588_TRIG_IN pulse width
tT1588TRIGH
2*tT1588CLK_MAX
——
ns
2
Note:
1. When TMR_CTRL[CKSEL]=00, the external TSEC_1588_CLK input is selected as the 1588 timer reference clock source,
with the timing defined in the Table above. The maximum value of tT1588CLK is defined in terms of TTX_CLK, which is the
maximum clock cycle period of the equivalent interface speed that the eTSEC1 port is running
.
When eTSEC1 is configured to operate in the parallel mode, the TTX_CLK is the maximum clock period of the
TSEC1_TX_CLK. When eTSEC1 operates in SGMII mode, the maximum value of tT1588CLK is defined in terms of the
recovered clock from SGMII SerDes. For example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK will be
2800, 280, and 56 ns respectively.
See the
MPC8536E PowerQUICC III Integrated Communications Processor Reference Manual for a description of
TMR_CTRL registers.
2. It need to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the
MPC8536E PowerQUICC
III Integrated Processor Reference Manual for a description of TMR_CTRL registers.
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