- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4052 > MPC8536EAVTAKGA (Freescale Semiconductor)MPU POWERQUICC III 783FCPBGA PDF資料下載
參數(shù)資料
| 型號： | MPC8536EAVTAKGA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 113/126頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC III 783FCPBGA |
| 標準包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 600MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應商設備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁當前第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁
Electrical Characteristics
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
87
This figure provides the AC test load for the I2C.
Figure 51. I2C AC Test Load
This figure shows the AC timing diagram for the I
2C bus.
Figure 52. I2C Bus AC Timing Diagram
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs—
Noise margin at the LOW level for each connected device
(including hysteresis)
VNL
0.1
× OVDD
—V
—
Noise margin at the HIGH level for each connected device
(including hysteresis)
VNH
0.2
× OVDD
—V
—
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I
2C timing
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the
high (H) state or setup time. Also, tI2SXKL symbolizes I
2C timing (I2) for the time that the data with respect to the start condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I
2C
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL signal)
to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition. When the
chip acts as the I2C bus master while transmitting, the chip drives both SCL and SDA. As long as the load on SCL and SDA
are balanced, the chip would not cause unintended generation of Start or Stop condition. Therefore, the 300 ns SDA output
delay time is not a concern. For details of the I2C frequency calculation, refer to
Determining the I2C Frequency Divider Ratio
for SCL (AN2919). Note that the I2C Source Clock Frequency is half of the CCB clock frequency for the chip.
3. The maximum tI2DVKH has only to be met if the chip does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
Table 64. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 63).
Parameter
Symbol 1
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
Sr
S
SDA
SCL
tI2CF
tI2SXKL
tI2CL
tI2CH
tI2DXKL, tI2OVKL
tI2DVKH
tI2SXKL
tI2SVKH
tI2KHKL
tI2PVKH
tI2CR
tI2CF
PS
相關PDF資料 |
PDF描述 |
|---|---|
| FSM44DSEF-S13 | CONN EDGECARD 88POS .156 EXTEND |
| AMM43DTAI-S189 | CONN EDGECARD 86POS R/A .156 SLD |
| AMM43DTMI-S189 | CONN EDGECARD 86POS R/A .156 SLD |
| AMM43DTBI-S189 | CONN EDGECARD 86POS R/A .156 SLD |
| AMC50DRYI-S93 | CONN EDGECARD 100PS DIP .100 SLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8536EAVTANG | 功能描述:微處理器 - MPU PQ38S 8536 SQUID RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8536EAVTANGA | 功能描述:微處理器 - MPU 8536 Encrypted RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8536EAVTAQG | 功能描述:微處理器 - MPU PQ38S 8536 SQUID RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8536EAVTAQGA | 功能描述:微處理器 - MPU 8536 Encrypted RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8536EAVTATGA | 功能描述:微處理器 - MPU 8536 Encrypted RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
發(fā)布緊急采購，3分鐘左右您將得到回復。