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參數(shù)資料
| 型號： | MPC8540CPX667JB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 5/24頁 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 667MHZ 783-FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 667MHz |
| 電壓： | 1.2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 784-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
| 配用： | MPC8540ADS-BGA-ND - BOARD APPLICATION DEV 8540 CWH-PPC-8540N-VE-ND - KIT EVAL SYSTEM MPC8540 |
MPC8540 PowerQUICC III Integrated Host Processor Product Brief, Rev. 0.1
Freescale Semiconductor
13
MPC8540 Architecture Overview
3.5 Programmable Interrupt Controller (PIC)
The programmable interrupt controller (PIC) implements the necessary functions to provide a flexible solution for
a general-purpose interrupt control. The interrupt controller unit implements the logic and programming structures
of the OpenPIC architecture. The MPC8540 interrupt controller unit supports its processor core and provides for 12
external interrupts (with fully nested interrupt delivery), 4 message interrupts, internal-logic driven interrupts, and
4 global high resolution timers. Up to 16 programmable interrupt priority levels are supported.
The interrupt controller unit can be bypassed to allow use of an external interrupt controller. Inter-processor interrupt
(IPI) communication is supported through the external interrupt and core reset signals of different processor cores
on the same device. The four IPIs are only used for self-interrupt in a single-core device such as the MPC8540.
3.6 I2C Controller
The inter-IC (IIC or I2C) bus is a two-wire, bidirectional serial bus that provides a simple and efficient method of
data exchange between devices. The synchronous, multiple master bus of the I
2C allows the MPC8540 to exchange
data with other I
2C devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and
LCDs. The two-wire bus (serial data SDA and serial clock SCL) minimizes the interconnections between devices.
The synchronous, multiple master bus of the I2C allows the connection of additional devices to the bus for expansion
and system development.
The I2C controller is a true multiple master bus; it includes collision detection and arbitration that prevents data
corruption if two or more masters attempt to control the bus simultaneously. This feature allows for complex
applications with multiprocessor control. The I
2C controller consists of a transmitter/receiver unit, a clocking unit,
and a control unit. The I2C unit supports general broadcast mode, and on-chip filtering rejects spikes on the bus.
3.7 Boot Sequencer
The MPC8540 provides a boot sequencer that uses the I2C interface to access an external serial ROM and loads the
data into the MPC8540’s configuration registers. The boot sequencer is enabled by a configuration pin sampled at
the negation of the MPC8540 hardware reset signal. If enabled, the boot sequencer holds the MPC8540 processor
core in reset until the boot sequence is complete. If the boot sequencer is not enabled, the processor core exits reset
and fetches boot code in default configurations.
3.8 Dual Universal Asynchronous Receiver/Transmitter (DUART)
The MPC8540 includes a DUART intended for use in maintenance, bringing-up, and debugging of systems. The
MPC8540 provides a standard four-wire handshake (SIN, SOUT, RTS, CTS) for each port. The DUART is a slave
interface. An interrupt is provided to the interrupt controller or optionally steered externally to allow device
handshakes. Interrupts are generated for transmit, receive, line status, and MODEM status.
The MPC8540 DUART supports full-duplex operation. It is compatible with the PC16450 and PC16550
programming models. Also, 16-byte FIFOs are supported for both the transmitter and the receiver.
Software programmable baud generators divide the system clock to generate a 16x clock. Serial interface data
formats (data length, parity, 1/1.5/2 STOP bit, baud rate) are also software selectable.
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| MPC8540CPX667JC | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC PQ37 Exented Temp RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MPC8540CVT667JB | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8540CVT667JC | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8540PX533JB | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8540PX667LB | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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