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參數(shù)資料
| 型號： | MPC8540PX533JB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 22/24頁 |
| 文件大小： | 0K |
| 描述： | MPU POWERQUICC 533MHZ 783FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 533MHz |
| 電壓： | 1.2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 784-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
MPC8540 PowerQUICC III Integrated Host Processor Product Brief, Rev. 0.1
Freescale Semiconductor
7
MPC8540 Architecture Overview
— Burstiness feature that permits counting of burst events with a programmable time between bursts
— Triggering and chaining capability
— Ability to generate an interrupt on overflow
System access port
— Uses JTAG interface and a TAP controller to access entire system memory map
— Supports 32-bit accesses to configuration registers
— Supports cache-line burst accesses to main memory
— Supports large block (4-Kbyte) uploads and downloads
— Supports continuous bit streaming of entire block for fast upload and download
IEEE 1149.1-compliant, JTAG boundary scan
783 FC-PBGA package
3
MPC8540 Architecture Overview
The following sections describe the major functional units of the MPC8540.
3.1 e500 Core Overview
The MPC8540 uses the e500 microprocessor core complex. The e500 core has an internal PLL that allows
independent optimization of the operating frequencies. The core frequencies are derived from either the primary PCI
clock input or an external oscillator. For information regarding the e500 core refer to the following documents:
EREF: A Reference for Freescale Semiconductor Book E and the e500 Core
PowerPC e500 Core Complex Reference Manual
PowerPC e500 Application Binary Interface User's Guide
NOTE
The e500 defines features that are not implemented on the MPC8540. It also
generally defines some features that the MPC8540 implements more specifically.
An understanding of these differences can be critical to ensure proper operation.
These differences are summarized in Section 5.14, “MPC8540 Implementation
Details,” in the MPC8540 Integrated Processor Reference Manual.
The following is a brief list of some of the key features of the e500 core complex:
Implements full Book E 32-bit architecture
Implements additional instructions, registers, and interrupts defined by APUs. The SPE provides an
extensive instruction set for 64-bit vector integer, single-precision floating-point, and fractional operations.
The SPFP APU provides scalar (32-bit) single-precision, floating-point instructions.
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