參數(shù)資料
型號(hào)： MPC8541EVTALF
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 28/88頁(yè)
文件大?。?/td> 0K
描述： IC MPU POWERQUICC III 783-FCPBGA
產(chǎn)品培訓(xùn)模塊： MPC8544E PowerQUICC™ III
標(biāo)準(zhǔn)包裝： 36
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 667MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤(pán)
配用： CWH-PPC-8540N-VE-ND - KIT EVAL SYSTEM MPC8540
MPC8541E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
34
Freescale Semiconductor
Local Bus
Table 31 describes the general timing parameters of the local bus interface of the MPC8541E with the DLL
bypassed.
Local bus clock to output high impedance for
LAD/LDP
LWE[0:1] = 00
tLBKHOZ2
—
2.8
ns
5, 9
LWE[0:1] = 11 (default)
4.2
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes
high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go
high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for DLL enabled mode.
3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN for DLL enabled to 0.4 × OVDD of the signal in
question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. The value of tLBOTOT is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of
local bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at OVDD/2.
8. Guaranteed by characterization.
9. Guaranteed by design.
Table 31. Local Bus General Timing Parameters—DLL Bypassed
Parameter
Configuration 7
Symbol 1
Min
Max
Unit
Notes
Local bus cycle time
—
tLBK
6.0
—
ns
2
Internal launch/capture clock to LCLK delay
—
tLBKHKT
1.8
3.4
ns
8
LCLK[n] skew to LCLK[m] or LSYNC_OUT
—
tLBKSKEW
—
150
ps
7, 9
Input setup to local bus clock (except
LUPWAIT)
—tLBIVKH1
5.2
—
ns
3, 4
LUPWAIT input setup to local bus clock
—
tLBIVKH2
5.1
—
ns
3, 4
Input hold from local bus clock (except
LUPWAIT)
—tLBIXKH1
–1.3
—
ns
3, 4
LUPWAIT input hold from local bus clock
—
tLBIXKH2
–0.8
—
ns
3, 4
LALE output transition to LAD/LDP output
transition (LATCH hold time)
—tLBOTOT
1.5
—
ns
6
Local bus clock to output valid (except
LAD/LDP and LALE)
LWE[0:1] = 00
tLBKLOV1
—0.5
ns
3
LWE[0:1] = 11 (default)
2.0
Local bus clock to data valid for LAD/LDP
LWE[0:1] = 00
tLBKLOV2
—0.7
ns
3
LWE[0:1] = 11 (default)
2.2
Table 30. Local Bus General Timing Parameters—DLL Enabled (continued)
Parameter
Configuration 7
Symbol 1
Min
Max
Unit
Notes
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