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    參數(shù)資料
    

    


    


    
型號：
MPC8541VTAJD

    

    
廠商：
Freescale Semiconductor

    

    
文件頁數(shù)：
78/88頁

    

    
文件大?。?/td>
0K

    

    
描述：
IC MPU POWERQUICC III 783-FCPBGA

    

    
標準包裝：
36

    

    
系列：
MPC85xx

    

    
處理器類型：
32-位 MPC85xx PowerQUICC III
    		

    

    
速度：
533MHz
    		

    

    
電壓：
1.2V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
封裝/外殼：
783-BBGA，F(xiàn)CBGA
    		

    

    
供應商設備封裝：
783-FCPBGA（29x29）
    		

    

    
包裝：
托盤
    		

    

    
配用：
CWH-PPC-8540N-VE-ND - KIT EVAL SYSTEM MPC8540
    		

    

    

    

	
    
    
    

    
    
	
    MPC8541E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
    8
    Freescale Semiconductor
    Electrical Characteristics
    2.1.1
    Absolute Maximum Ratings
    Table 1 provides the absolute maximum ratings.
    2.1.2
    Power Sequencing
    The MPC8541Erequires its power rails to be applied in a specific sequence in order to ensure proper device
    operation. These requirements are as follows for power up:
    1. VDD, AVDDn
    2. GVDD, LVDD, OVDD (I/O supplies)
    Table 1. Absolute Maximum Ratings 1
    Characteristic
    Symbol
    Max Value
    Unit
    Notes
    Core supply voltage
    VDD
    –0.3 to 1.32
    0.3 to 1.43 (for 1 GHz only)
    V
    PLL supply voltage
    AVDD
    –0.3 to 1.32
    0.3 to 1.43 (for 1 GHz only)
    V
    DDR DRAM I/O voltage
    GVDD
    –0.3 to 3.63
    V
    Three-speed Ethernet I/O, MII management voltage
    LVDD
    –0.3 to 3.63
    –0.3 to 2.75
    V
    CPM, PCI, local bus, DUART, system control and power
    management, I2C, and JTAG I/O voltage
    OVDD
    –0.3 to 3.63
    V
    3
    Input voltage
    DDR DRAM signals
    MVIN
    –0.3 to (GVDD + 0.3)
    V
    2, 5
    DDR DRAM reference
    MVREF
    –0.3 to (GVDD + 0.3)
    V
    2, 5
    Three-speed Ethernet signals
    LVIN
    –0.3 to (LVDD + 0.3)
    V
    4, 5
    CPM, Local bus, DUART,
    SYSCLK, system control and
    power management, I2C, and
    JTAG signals
    OVIN
    –0.3 to (OVDD + 0.3)1
    V
    5
    PCI
    OVIN
    –0.3 to (OVDD + 0.3)
    V
    6
    Storage temperature range
    TSTG
    –55 to 150
    °C
    Notes:
    1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
    functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
    permanent damage to the device.
    2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
    power-on reset and power-down sequences.
    3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
    power-on reset and power-down sequences.
    4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
    power-on reset and power-down sequences.
    5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
    6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
    shown in Figure 3.
    
    
    
    
    
    


    


    

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