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  • 參數(shù)資料
    型號(hào): MPC8544AVTARJA
    廠商: Freescale Semiconductor
    文件頁數(shù): 16/117頁
    文件大?。?/td> 0K
    描述: IC MPU POWERQUICC III 783-FCBGA
    標(biāo)準(zhǔn)包裝: 36
    系列: MPC85xx
    處理器類型: 32-位 MPC85xx PowerQUICC III
    速度: 1.067GHz
    電壓: 0.95 V ~ 1.05 V
    安裝類型: 表面貼裝
    封裝/外殼: 783-BBGA,F(xiàn)CBGA
    供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
    包裝: 托盤
    MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
    112
    Freescale Semiconductor
    System Design Information
    Figure 69 shows the JTAG interface connection.
    Figure 69. JTAG Interface Connection
    HRESET
    From Target
    Board Sources
    COP_HRESET
    13
    COP_SRESET
    SRESET
    NC
    11
    COP_VDD_SENSE2
    6
    5
    15
    10
    Ω
    10 k
    Ω
    10 k
    Ω
    COP_CHKSTP_IN
    CKSTP_IN
    8
    COP_TMS
    COP_TDO
    COP_TDI
    COP_TCK
    TMS
    TDO
    TDI
    9
    1
    3
    4
    COP_TRST
    7
    16
    2
    10
    12
    (if any)
    COP
    Hea
    d
    er
    14 3
    Notes:
    3. The KEY location (pin 14) is not physically present on the COP header.
    10 k
    Ω
    TRST1
    10 k
    Ω
    10 k
    Ω
    10 k
    Ω
    CKSTP_OUT
    COP_CHKSTP_OUT
    3
    13
    9
    5
    1
    6
    10
    15
    11
    7
    16
    12
    8
    4
    KEY
    No pin
    COP Connector
    Physical Pinout
    1
    2
    NC
    SRESET
    2. Populate this with a 10-
    Ω resistor for short-circuit/current-limiting protection.
    NC
    OVDD
    10 k
    Ω
    HRESET1
    in order to fully control the processor as shown here.
    4. Although pin 12 is defined as a No Connect, some debug tools may use pin 12 as an additional GND pin for
    1. The COP port and target board should be able to independently assert HRESET and TRST to the processor
    improved signal integrity.
    TCK
    4
    5
    5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL
    testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be
    10 k
    Ω
    6
    6. Asserting SRESET causes a machine check interrupt to the e500 core.
    A
    B
    closed to position B.
    10 k
    Ω
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