參數(shù)資料
型號: MPC8544ECVTALFA
廠商: Freescale Semiconductor
文件頁數(shù): 44/117頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC III 783-FCBGA
標準包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 667MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應商設備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
32
Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
8.5.2
GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
8.5.2.1
GMII Transmit AC Timing Specifications
Table 30 provides the GMII transmit AC timing specifications.
Figure 13 shows the GMII transmit AC timing diagram.
Figure 13. GMII Transmit AC Timing Diagram
Table 30. GMII Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
GTX_CLK clock period
tGTX
8.0
—ns—
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
tGTKHDX
0.2
5.0
ns
2
GTX_CLK data clock rise time (20%-80%)
tGTXR
——
1.0
ns
GTX_CLK data clock fall time (80%-20%)
tGTXF
——
1.0
ns
Notes:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing
(GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching
the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock
reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention
is used with the appropriate letter: R (rise) or F (fall).
2. Data valid tGTKHDV to GTX_CLK Min setup time is a function of clock period and max hold time (Min setup = cycle time – Max
delay).
GTX_CLK
TXD[7:0]
tGTKHDX
tGTX
tGTXH
tGTXR
tGTXF
tGTKHDV
TX_EN
TX_ER
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