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  • 參數(shù)資料
    型號: MPC8545PXANGB
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 800 MHz, MICROPROCESSOR, PBGA783
    封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
    文件頁數(shù): 139/142頁
    文件大小: 1504K
    代理商: MPC8545PXANGB
    MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
    96
    Freescale Semiconductor
    Package Description
    Analog Signals
    MVREF
    A18
    I
    Reference
    voltage signal
    for DDR
    MVREF
    SD_IMP_CAL_RX
    L28
    I
    200
    Ω to
    GND
    SD_IMP_CAL_TX
    AB26
    I
    100
    Ω to
    GND
    SD_PLL_TPA
    U26
    O
    24
    Notes:
    1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
    local bus controller section, and is not mentioned in the DMA section even though the pin also functions as DMA_REQ2.
    2. Recommend a weak pull-up resistor (2–10 k
    Ω) be placed on this pin to OVDD.
    3. A valid clock must be provided at POR if TSEC4_TXD[2] is set = 1.
    4. This pin is an open drain signal.
    5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
    reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
    Ω pull-down resistor. However, if the
    signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at
    reset, then a pullup or active driver is needed.
    6. Treat these pins as no connects (NC) unless using debug address functionality.
    7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k
    Ω pull-up or pull-down
    8. The value of LALE, LGPL2, and LBCTL at reset set the e500 core clock to CCB clock PLL ratio. These pins require 4.7-k
    Ω
    pull-up or pull-down resistors. See the Section 19.3, “e500 Core PLL Ratio.
    9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
    because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.
    10.This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI
    operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit
    PCI device. Refer to the
    PCI Specification.
    11.This output is actively driven during reset rather than being three-stated during reset.
    12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.
    13.These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking
    and regulation.
    14.Internal thermally sensitive resistor.
    15.No connections should be made to these pins if they are not used.
    16.These pins are not connected for any use.
    17.PCI specifications recommend that a weak pull-up resistor (2–10 k
    Ω) be placed on the higher order pins to OVDD when using
    64-bit buffer mode (pins PCI_AD[63:32] and PCI1_C_BE[7:4]).
    19.If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state
    during reset.
    20.This pin is only an output in FIFO mode when used as Rx flow control.
    24.Do not connect.
    Table 67. MPC8548E Pinout Listing (continued)
    Signal
    Package Pin Number
    Pin Type
    Power
    Supply
    Notes
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