參數(shù)資料
型號: MPC8548EHXAVJB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1500 MHz, MICROPROCESSOR, CBGA783
封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, CERAMIC, BGA-783
文件頁數(shù): 78/142頁
文件大?。?/td> 1504K
代理商: MPC8548EHXAVJB
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
40
Freescale Semiconductor
Ethernet Management Interface Electrical Characteristics
9.2
MII Management AC Electrical Specifications
Table 37 provides the MII management AC timing specifications.
Input high current (OVDD = Max, VIN
1 = 2.1 V)
IIH
—40
μA
Input low current (OVDD = Max, VIN = 0.5 V)
IIL
–600
μA
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
Table 37. MII Management AC Timing Specifications
At recommended operating conditions with OVDD is 3.3 V ± 5%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
MDC frequency
fMDC
0.72
2.5
8.3
MHz
2, 3,4
MDC period
tMDC
120.5
1389
ns
MDC clock pulse width high
tMDCH
32
ns
MDC to MDIO valid
tMDKHDV
16
× tCCB
——
ns
5
MDC to MDIO delay
tMDKHDX
(16 *
tptb_clk*8)-3
—(16 *
tptb_clk*8)+3
ns
5
MDIO to MDC setup time
tMDDVKH
5—
ns
MDIO to MDC hold time
tMDDXKH
0—
ns
MDC rise time
tMDCR
10
ns
4
MDC fall time
tMDHF
—10
ns
4
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two
letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing
(MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state
or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (fCCB). The actual ECn_MDC output
clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of
MPC8548E’s MIIMCFG register, based
on the platform (CCB) clock running for the device. The formula is: Platform Frequency (CCB)/(2*Frequency Divider determined by
MIICFG[MgmtClk] encoding selection). For example, if MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, fMDC
= 533/(2*4*8) = 533/64 = 8.3 MHz. That is, for a system running at a particular platform frequency (fCCB), the ECn_MDC output clock
frequency can be programmed between maximum fMDC = fCCB/64 and minimum fMDC = fCCB/448. Refer to MPC8572E reference manual’s
MIIMCFG register section for more detail.3.The maximum ECn_MDC output clock frequency is defined based on the maximum platform
frequency for
MPC8548E (533 MHz) divided by 64, while the minimum ECn_MDC output clock frequency is defined based on the minimum
platform frequency for
MPC8548E (333 MHz) divided by 448, following the formula described in Note 2 above.
4. Guaranteed by design.
5. tCCB is the platform (CCB) clock period.
Table 36. MII Management DC Electrical Characteristics (continued)
Parameter
Symbol
Min
Max
Unit
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