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  • 參數(shù)資料
    型號: MPC8548EPXAQH
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783
    封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
    文件頁數(shù): 121/142頁
    文件大?。?/td> 1504K
    代理商: MPC8548EPXAQH
    MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
    8
    Freescale Semiconductor
    Overview
    — Memory prefetching of PCI read accesses
    — Supports posting of processor-to-PCI and PCI-to-memory writes
    — PCI 3.3-V compatible
    — Selectable hardware-enforced coherency
    Serial RapidIO interface unit
    — Supports RapidIO Interconnect Specification, Revision 1.2
    — Both 1x and 4x LP-serial link interfaces
    — Long- and short-haul electricals with selectable pre-compensation
    — Transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per lane
    — Auto detection of 1x- and 4x-mode operation during port initialization
    — Link initialization and synchronization
    — Large and small size transport information field support selectable at initialization time
    — 34-bit addressing
    — Up to 256 bytes data payload
    — All transaction flows and priorities
    — Atomic set/clr/inc/dec for read-modify-write operations
    — Generation of IO_READ_HOME and FLUSH with data for accessing cache-coherent data at
    a remote memory system
    — Receiver-controlled flow control
    — Error detection, recovery, and time-out for packets and control symbols as required by the
    RapidIO specification
    — Register and register bit extensions as described in part VIII (Error Management) of the
    RapidIO specification
    — Hardware recovery only
    — Register support is not required for software-mediated error recovery.
    — Accept-all mode of operation for fail-over support
    — Support for RapidIO error injection
    — Internal LP-serial and application interface-level loopback modes
    — Memory and PHY BIST for at-speed production test
    RapidIO-compatible message unit
    — 4 Kbytes of payload per message
    — Up to sixteen 256-byte segments per message
    — Two inbound data message structures within the inbox
    — Capable of receiving three letters at any mailbox
    — Two outbound data message structures within the outbox
    — Capable of sending three letters simultaneously
    — Single segment multicast to up to 32 devIDs
    — Chaining and direct modes in the outbox
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
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