參數(shù)資料
型號: MPC8555ECPXAJE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù): 84/88頁
文件大?。?/td> 1110K
代理商: MPC8555ECPXAJE
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
85
Document Revision History
18 Document Revision History
Table 51 provides a revision history for this hardware specification.
Rev. No.
Date
Substantive Change(s)
4.2
1/2008
Added “Note: Rise/Fall Time on CPM Input Pins” and following note text to Section 10.2, “CPM AC
4.1
7/2007
4
12/2006
Updated back page information.
3.2
11/2006
3.1
10/2005
Added footnote 2 about junction temperature in Table 4.
Added max. power values for 1000 MHz core frequency in Table 4.
Removed Figure 3, “Maximum AC Waveforms on PCI Interface for 3.3-V Signaling.”
Modified note to tLBKSKEW from 8 to 9 in Table 30.
Changed tLBKHOZ1 and tLBKHOV2 values inTable 30.
Added note 3 to tLBKHOV1 in Table 30.
Added note 3 to tLBKLOV1 in Table 31.
Modified values for tLBKHKT, tLBKLOV1, tLBKLOV2, tLBKLOV3, tLBKLOZ1, and tLBKLOZ2 in Table 31.
Changed Input Signals: LAD[0:31]/LDP[0:3] in Figure 21.
Modified note for signal CLK_OUT in Table 43.
PCI1_CLK and PCI2_CLK changed from I/O to I in Table 43.
Added column for Encryption Acceleration in Table 52.
3
8/2005
Modified max. power values in Table 4.
Modified notes for signals TSEC1_TXD[3:0], TSEC2_TXD[3:0], TRIG_OUT/READY, MSRCID4,
CLK_OUT, and MDVAL in Table 43.
2
8/2005
Previous revision’s history listed incorrect cross references. Table 2 is now correctly listed as
Table 27 and Table 38 is now listed as Table 31.
Modified min and max values for tDDKHMP in Table 14.
1
6/2005
Changed LVdd to OVdd for the supply voltage Ethernet management interface in Table 27.
Modified footnote 4 and changed typical power for the 1000 MHz core frequency inTable 4.
Corrected symbols for body rows 9–15, effectively changing them from a high state to a low state
0
6/2005
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