1. 參數(shù)資料
    型號: MPC8555PXALDX
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
    封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
    文件頁數(shù): 23/88頁
    文件大?。?/td> 1244K
    代理商: MPC8555PXALDX
    MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specifications, Rev. 4
    Freescale Semiconductor
    3
    Overview
    Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
    802.11i, iSCSI, and IKE processing. The Security Engine contains 4 Crypto-channels, a Controller,
    and a set of crypto Execution Units (EUs). The Execution Units are:
    — Public Key Execution Unit (PKEU) supporting the following:
    – RSA and Diffie-Hellman
    – Programmable field size up to 2048-bits
    – Elliptic curve cryptography
    – F2m and F(p) modes
    – Programmable field size up to 511-bits
    — Data Encryption Standard Execution Unit (DEU)
    – DES, 3DES
    – Two key (K1, K2) or Three Key (K1, K2, K3)
    – ECB and CBC modes for both DES and 3DES
    — Advanced Encryption Standard Unit (AESU)
    – Implements the Rinjdael symmetric key cipher
    – Key lengths of 128, 192, and 256 bits.Two key
    – ECB, CBC, CCM, and Counter modes
    — ARC Four execution unit (AFEU)
    Implements a stream cipher compatible with the RC4 algorithm
    40- to 128-bit programmable key
    — Message Digest Execution Unit (MDEU)
    – SHA with 160-bit or 256-bit message digest
    – MD5 with 128-bit message digest
    – HMAC with either algorithm
    — Random Number Generator (RNG)
    — 4 Crypto-channels, each supporting multi-command descriptor chains
    Static and/or dynamic assignment of crypto-execution units via an integrated controller
    Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes
    High-performance RISC CPM operating at up to 333 MHz
    — CPM software compatibility with previous PowerQUICC families
    — One instruction per clock
    — Executes code from internal ROM or instruction RAM
    — 32-bit RISC architecture
    — Tuned for communication environments: instruction set supports CRC computation and bit
    manipulation.
    — Internal timer
    — Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and
    virtual DMA channels for each peripheral controller
    — Handles serial protocols and virtual DMA
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    MPC8555EPXALFX 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
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