參數(shù)資料
型號: MPC855TCVR66D4
廠商: Freescale Semiconductor
文件頁數(shù): 12/15頁
文件大小: 0K
描述: IC MPU POWERQUICC 66MHZ 357-PBGA
標準包裝: 44
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 66MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應商設(shè)備封裝: 357-PBGA(25x25)
包裝: 托盤
6
MPC855T Communications Controller Technical Summary
MOTOROLA
MPC855T Key Features
— QMC multichannel features
– Up to 32 independent communication channels on a single SCC
– Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots
– Supports either transparent or HDLC protocols for each channel
– Independent transmit and receive buffer descriptors and event/interrupt reporting for each
channel
— Two SMCs (serial management channels)
– UART
– Transparent
– General circuit interface (GCI) controller
– May be connected to the time-division-multiplexed (TDM) channels
— One SPI (serial peripheral interface)
– Supports master and slave modes
– Supports multimaster operation on the same bus
— One I2C (inter-integrated circuit) port
– Supports master and slave modes
– Multimaster environment support
— Time slot assigner (TSA) supporting TDMa only
– Allows SCC and SMCs to run in multiplexed and/or nonmultiplexed operation
– Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user dened
– 1- or 8-bit resolution
– Allows independent transmit and receive routing, frame syncs, clocking
– Allows dynamic changes
– May be internally connected to three serial channels (one SCC and two SMCs)
— Parallel interface port
– Centronics interface support
– Supports fast connection between compatible ports on MPC860 or MC68360
— Low power support
– Full-on–all units fully powered
– Doze–core functional units disabled except time base, decrementer, PLL, memory
controller, RTC, and CPM in low-power standby
– Sleep–all units disabled except RTC and PIT, PLL active for fast wake-up
– Deep sleep–all units disabled including PLL except RTC and PIT
– Low-power STOP mode provides lowest power dissipation
— Debug interface
– Eight comparators: four operate on instruction address, two operate on data address, and
two operate on data
– Supports conditions: =
≠ < >
– Each watchpoint can generate a breakpoint internally
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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