參數(shù)資料
型號(hào): MPC855TZQ50D4R2
廠商: Freescale Semiconductor
文件頁數(shù): 28/78頁
文件大?。?/td> 0K
描述: IC MPU PWRQUICC 50MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 180
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 50MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 帶卷 (TR)
MPC860 PowerQUICC Family Hardware Specifications, Rev. 9
34
Freescale Semiconductor
Bus Signal Timing
Table 9 shows the PCMCIA timing for the MPC860.
Table 9. PCMCIA Timing
Num
Characteristic
33 MHz
40 MHz
50 MHz
66 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
P44
A(0:31), REG valid to PCMCIA Strobe
asserted1
1 PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the
PCMCIA current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the
PSL timer expiration. See Chapter 16, “PCMCIA Interface,” in the MPC860 PowerQUICC Family
User’s Manual.
20.73
16.75
13.00
9.36
ns
P45
A(0:31), REG valid to ALE negation1
28.30
23.00
18.00
13.15
ns
P46
CLKOUT to REG valid
7.58
15.58
6.25
14.25
5.00
13.00
3.79
11.84
ns
P47
CLKOUT to REG invalid
8.58
7.25
6.00
4.84
ns
P48
CLKOUT to CE1, CE2 asserted
7.58
15.58
6.25
14.25
5.00
13.00
3.79
11.84
ns
P49
CLKOUT to CE1, CE2 negated
7.58
15.58
6.25
14.25
5.00
13.00
3.79
11.84
ns
P50
CLKOUT to PCOE, IORD, PCWE, IOWR
assert time
11.00
11.00
11.00
ns
P51
CLKOUT to PCOE, IORD, PCWE, IOWR
negate time
2.00
11.00
2.00
11.00
2.00
11.00
2.00
11.00
ns
P52
CLKOUT to ALE assert time
7.58
15.58
6.25
14.25
5.00
13.00
3.79
10.04
ns
P53
CLKOUT to ALE negate time
15.58
14.25
13.00
11.84
ns
P54
PCWE, IOWR negated to D(0:31) invalid1
5.58
4.25
3.00
1.79
ns
P55
WAITA and WAITB valid to CLKOUT rising
edge1
8.00
8.00
8.00
8.00
ns
P56
CLKOUT rising edge to WAITA and WAITB
invalid1
2.00
2.00
2.00
2.00
ns
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