參數(shù)資料
型號: MPC8560CPXALFB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù): 106/108頁
文件大?。?/td> 2170K
代理商: MPC8560CPXALFB
MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
Freescale Semiconductor
97
System Design Information
tightly regulated source of power. Therefore, it is recommended that the system designer place at least one
decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins of the MPC8560. These decoupling capacitors
should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND power planes in the PCB, utilizing
short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape
pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology) capacitors
should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the
VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk
capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary.
They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested
bulk capacitors—100–330 F (AVX TPS tantalum or Sanyo OSCON).
17.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level.
Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high inputs should
be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of the
MPC8560.
17.5 Output Buffer DC Impedance
The MPC8560 drivers are characterized over process, voltage, and temperature. There are two driver types: a
push-pull single-ended driver (open drain for I2C) for all buses except RapidIO, and a current-steering differential
driver for the RapidIO port.
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND.
Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 59). The output impedance is
the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1
is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the
resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.
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